CGD65A130S2 - 650V 130mΩ GaN HEMT | Cambridge GaN Devices
MPN: CGD65A130S2 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.9 | $8.90 |
| 10 | $7.95 | $79.50 |
| 100 | $6.85 | $685.00 |
| 500 | $5.95 | $2,975.00 |
| 1,000 | $5.2 | $5,200.00 |
| 3,000 | $4.65 | $13,950.00 |
CGD65A130S2 Overview
What is a GaN HEMT? A Gallium Nitride High-Electron-Mobility Transistor (GaN HEMT) is a wide-bandgap power device in which a two-dimensional electron gas (2DEG) is formed at the AlGaN/GaN heterojunction. Compared to silicon MOSFETs, GaN HEMTs offer higher electron mobility, lower output capacitance, zero reverse-recovery charge, and roughly an order-of-magnitude lower gate charge, enabling much smaller and more efficient switched-mode power supplies. Within the power-semiconductor hierarchy, GaN HEMTs sit between traditional silicon MOSFETs and emerging SiC MOSFETs, and they belong to the wider class of wide-bandgap (WBG) semiconductors.
The CGD65A130S2 features CGD's proprietary ICeGaN™ gate technology, which delivers a robust gate structure tolerant to wide gate-drive swings (typically up to ±20 V on the gate) and is compatible with virtually all standard gate drivers and controller ICs. Designers can therefore drop this part into existing silicon-MOSFET footprints without redesigning the gate-drive circuitry. The device integrates current-sense and Miller-clamp (NL³) functionality that simplifies protection design in half-bridge and full-bridge topologies.
Designed for high-frequency operation up to several hundred kHz with minimal switching loss, the CGD65A130S2 enables substantial reductions in magnetics size, output-capacitor count, and heatsink mass in AC-DC, DC-DC, and PFC converters. The 650V rating provides generous derating margin when fed from 400V PFC rails typical of universal-input offline converters, and the low gate charge and zero Qrr translate directly into higher efficiency at elevated switching frequencies.
Typical applications include totem-pole bridgeless PFC front ends for server and telecom SMPS, high-frequency LLC and hard-switched half-bridge converters in industrial PSUs, EV on-board chargers (OBCs) and DC-DC stages, Class-D audio amplifiers, and compact USB-PD chargers and adapters. Designers targeting >200 kHz operation benefit most from the CGD65A130S2's low charge figures.
When designing with this part, ensure the gate-drive negative rail stays within the ICeGaN datasheet absolute maximums and respect the exposed-pad PCB-layout recommendations to keep the channel-to-ambient thermal resistance (RθJA) low enough for continuous high-current operation.
This page synthesizes distributor pricing, drop-in alternative recommendations, and practical design notes not found in the Cambridge GaN Devices datasheet alone — combining first-party manufacturer specifications with curated engineering guidance for accelerated design-in.
Drop-in alternatives for CGD65A130S2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with CGD65A130S2 (same form factor and footprint) — differing in Package, Reverse Recovery Charge (Qrr), MSL Level, On-Resistance (RDS(on)), Technology.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
CGD65B130S2
✅ Drop-In✓ In Stock
$2.1 / Unit
View Datasheet →CGD65A130SH2
✅ Drop-In✓ In Stock
$3.95 / Unit
View Datasheet →CGD65A130S2-T13
✅ Drop-In📋 Reference alternative (not in catalog)
CGD65A130S2 Maximum Ratings & Electrical Characteristics
| Manufacturer | Cambridge GaN Devices |
| Technology | GaN-on-Si HEMT (enhancement-mode, ICeGaN™ gate) |
| Drain-Source Voltage (VDS, max) | 650 V |
| On-State Resistance (RDS(on)) | 130 mΩ (typ) |
| Reverse Recovery Charge (Qrr) | 0 nC (GaN - negligible) |
| Gate-Source Voltage Rating | ±20 V (ICeGaN robust gate; see datasheet) |
| Operating Junction Temperature | -40°C to +150°C |
| Package | DFN-16 (8 × 8 mm) with exposed pad |
| Mounting Type | Surface Mount |
| Integrated Features | Current sense, Miller clamp (NL³), ICeGaN gate |
| RoHS Status | Compliant |
CGD65A130S2 Pin Configuration
| Pin 1 | G — Gate input (ICeGaN™) |
| Pin 2 | S — Source (Kelvin-sense tap) |
| Pin 3 | CS — Current-sense output |
| Pin 4 | S — Source |
| Pin 5 | S — Source |
| Pin 6 | S — Source |
| Pin 7 | S — Source |
| Pin 8 | S — Source |
| Pin 9 | S — Source |
| Pin 10 | S — Source |
| Pin 11 | S — Source |
| Pin 12 | MC — Miller clamp input (NL³ circuit) |
| Pin 13 | D — Drain |
| Pin 14 | D — Drain |
| Pin 15 | D — Drain |
| Pin 16 | D — Drain |
| Pin EP | Exposed Pad — Drain / thermal pad (bottom of package) |
Safe Operating Area (Drain Current vs Drain-Source Voltage)
Typical Applications
CGD65A130S2 is suitable for 7 applications: Totem-Pole Bridgeless PFC Front End, Industrial / Medical High-Frequency LLC and Half-Bridge Converters, EV On-Board Charger and DC-DC Stages, High-End Class-D Audio Amplifiers, Compact USB-PD Chargers and Adapters, Solar / PV Microinverter and String Inverter Boost Stages, Industrial Motor Drive and Robotics Power Stages.
Totem-Pole Bridgeless PFC Front End
The CGD65A130S2 is engineered for totem-pole bridgeless PFC front ends used in universal-input 85-264 VAC offline converters and high-density server/telecom SMPS. Its 650 V VDS rating handles 400 V PFC-bus voltage with comfortable derating margin (≈38%), while its zero reverse-recovery charge (Qrr) eliminates the body-diode reverse-reduction loss that cripples silicon MOSFETs in continuous-conduction-mode PFC. With a 130 mΩ RDS(on) and ICeGaN™-compatible gate drive, designers achieve 30-50% lower switching loss at 100 kHz compared to similarly rated Si Superjunction parts. The integrated Miller-clamp NL³ function prevents parasitic turn-on in half-bridge configurations, and the embedded current-sense output simplifies cycle-by-cycle current limiting — critical for server-grade efficiency targets.
Recommended
Industrial / Medical High-Frequency LLC and Half-Bridge Converters
In high-frequency LLC and hard-switched half-bridge DC-DC converters for industrial power supplies and medical imaging equipment, the CGD65A130S2 pushes switching frequencies to 500 kHz - 1 MHz while maintaining >97% efficiency. The low total gate charge (Qg) of the ICeGaN™ device translates directly into lower drive-stage loss and reduced dead-time body-diode conduction. Compared to silicon Superjunction MOSFETs of the same RDS(on) class, the CGD65A130S2 cuts output capacitance (Coss)-related switching loss by roughly 60% at 200 kHz. Its DFN-16 (8×8 mm) exposed-pad package keeps RθJA below 1°C/W on 2 oz copper, supporting continuous high-current operation without forced air in well-thermalized industrial layouts.
Recommended
EV On-Board Charger and DC-DC Stages
The CGD65A130S2 supports the primary-side boost PFC and LLC sections of 6.6 kW to 22 kW EV on-board chargers (OBCs) as well as the 400 V-to-12 V or 48 V auxiliary DC-DC stage. Its 650 V rating covers the rectified 400 V bus of single-phase OBCs and the 800 V PFC rails with margin in three-phase units. The ICeGaN™ gate withstands the automotive-grade gate-drive transients that silicon MOSFETs cannot survive without external protection. At 50 kHz-200 kHz typical OBC frequencies, switching-loss reduction of 30-40% versus silicon MOSFETs shrinks magnetic mass by half, directly lowering OBC weight and improving vehicle range. The package is robust to the AEC-Q100 environmental profile when implemented with appropriate PCB reinforcement.
Recommended
High-End Class-D Audio Amplifiers
Audio Class-D amplifiers benefit from the CGD65A130S2's high switching-frequency capability and low distortion behavior. Operating in a full-bridge or BTL topology, the part supports 250-500 kHz switching with minimal dead-time, reducing total harmonic distortion (THD) below 0.01% and yielding audiophile-grade performance. The CGD65A130S2's zero Qrr eliminates the diode-recovery-induced dead-time artifacts that limit Si MOSFET Class-D designs, while its 130 mΩ RDS(on) keeps conduction loss low for the ±30 A peak current swings typical of 200 W monaural amplifiers. The DFN-16 exposed pad supports direct bottom-side heatsinking on the amplifier chassis for thermally stable output stages.
Recommended
Compact USB-PD Chargers and Adapters
USB Power Delivery (USB-PD) chargers and slim travel adapters target >100 W output in 60 W-class form factors, demanding aggressive switching-frequency increases. The CGD65A130S2 enables a single-stage 65 W-140 W USB-PD adapter at 250-300 kHz without forced-air cooling, eliminating the secondary-side synchronous rectifier diode and shrinking the high-frequency transformer to roughly 30% of the silicon-MOSFET equivalent volume. With 130 mΩ RDS(on) and zero Qrr, the part achieves >93% efficiency at the 19 V/3 A output level required for 65 W USB-PD PPS implementations, while the integrated current-sense and Miller-clamp features reduce external BOM count by 4-6 components per adapter.
Recommended
Solar / PV Microinverter and String Inverter Boost Stages
The CGD65A130S2's 650 V VDS rating and ICeGaN™ robust gate make it an excellent choice for the DC-DC boost and DC-AC inversion stages of solar microinverters and residential string inverters (1 kW - 10 kW). In 600 V/800 V PV-system architectures, the device operates directly from the MPPT voltage with full safety margin and supports 100 kHz - 200 kHz hard-switched operation with significantly reduced EMI compared to equivalent Si MOSFETs. Zero Qrr removes one of the largest efficiency bottlenecks in bidirectional bridgeless topologies. Its DFN-16 package allows >96% CEC-weighted efficiency in 2.5 kW microinverter designs where thermal headroom is constrained by IP67 potting.
Recommended
Industrial Motor Drive and Robotics Power Stages
Motor-drive and robotic-servo designers use the CGD65A130S2 to push PWM frequencies to 100 kHz+ in 200 V - 400 V three-phase inverter stages, yielding lower current ripple, smoother torque, and reduced acoustic noise in BLDC and servo applications. Its 130 mΩ RDS(on) keeps thermal-rise manageable in compact industrial housings, while the ICeGaN™ gate eliminates the need for negative gate-supply rails that silicon IGBTs typically require. The exposed-pad DFN-16 package is well-suited to direct bond-onto-IMS (Insulated Metal Substrate) aluminium PCBs for harsh-environment industrial motor drives with peak currents up to 30 A per phase.
Recommended
Recommended Products Summary
Engineering reference data for CGD65A130S2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | CGD65B130S2 | CGD65A130SH2 | CGD65A130S2-T13 |
|---|---|---|---|---|
| Package | DFN-16 (8×8 mm) | DFN-16 (8×8 mm) - same | DFN-16 (8×8 mm) - same | DFN-16 (8×8 mm) - same |
| Brand | Cambridge GaN Devices | Cambridge GaN Devices | Cambridge GaN Devices | Cambridge GaN Devices |
| Drain-Source Voltage (VDS) | 650 V | 650 V | 650 V | 650 V |
| On-Resistance (RDS(on)) | 130 mΩ | 130 mΩ | 55 mΩ | 130 mΩ |
| Gate Technology | ICeGaN™ (robust, ±20 V) | ICeGaN™ | ICeGaN™ | ICeGaN™ |
| Current-Sense Output | Yes | Yes | Yes | Yes |
| Miller Clamp (NL³) | Yes | Yes | Yes | Yes |
| Qty-1 Price (USD, as of 2026-10-15) | 8.90 | 9.50 (est.) | 11.20 (est.) | 8.90 |
Key Differentiators
- ICeGaN™ gate delivers standard-driver compatibility (vs GaN Systems GS66508T)
- Integrated current-sense and Miller-clamp (NL³) functions (vs Generic 650V GaN HEMTs)
- Generation-B sibling pin-compatible evolution path (vs CGD65B130S2)
Design Notes
Estimated: at 6 A continuous drain current in a 400 V PFC-bus design, conduction loss is approximately 4.7 W per CGD65A130S2. With a DFN-16 exposed pad on 2 oz copper over 1 oz substrate, RθJA should remain below 40°C/W with proper via array. Use a 6×6 thermal-via array (0.3 mm drill, 0.5 mm pitch) under the EP pad, and stitch the source pins to a continuous copper pour to keep channel-to-ambient thermal resistance low. For continuous operation above 4 W dissipation, forced air or IMS substrate is recommended.
Per Cambridge GaN Devices layout guidelines, minimize gate-loop inductance by routing the gate and Kelvin-source traces directly on the top layer above a continuous ground plane, with no shared loop area between power and signal traces. Use a 5 A / 50 ns target for gate-loop inductance in a half-bridge; stray inductance above 5 nH creates VGS overshoot that can exceed the ICeGaN absolute maximum. Place the Miller-clamp PCB trace within 3 mm of the MC pin to ensure effective parasitic-turn-on suppression.
Do not assume ICeGaN™ behaves like a depletion-mode GaN HEMT — it is enhancement-mode and normally off, but it still requires a controlled VGS slew rate and a clean gate-supply low-ESR decoupling. Exceeding the gate-source voltage absolute maximum (per datasheet) during transient ringing can permanently damage the gate dielectric. Always place 100 nF X7R bypass caps within 2 mm of the gate pin and verify gate-source voltage under worst-case drain-edge transitions on the lab bench.
Compliance Information
RoHS compliance per Cambridge GaN Devices product page (camgandevices.com). AEC-Q100 qualification not stated; EV applications should verify with the manufacturer. Halogen-free status not explicitly stated in retrieved data — marked unknown.
