EP20K600CB672C8N - APEX-20KC FPGA 24K LE 672-BGA | Intel
MPN: EP20K600CB672C8N ✗ Cuối đờiEP20K600CB672C8N Tóm tắt
An FPGA (Field-Programmable Gate Array) is a semiconductor integrated circuit built from an array of configurable logic blocks, embedded memory, routing interconnect and I/O cells that the designer programs after manufacture. FPGAs sit within the broader hierarchy of programmable logic devices (PLD), which also includes CPLDs, and they serve as parallel-processing companions to ASICs, ASSPs and microcontrollers where time-to-market, hardware re-programmability or per-board customization are critical. APEX-20KC parts are considered high-density members of the APEX-20K family, designed for datapath-intensive designs that combine wide datapaths, on-chip memory and high I/O counts.
Key features include MultiVolt I/O support (1.8 V, 2.5 V and 3.3 V interfaces with a 2.5 V core), PCI-SIG compliant 3.3 V PCI bus operation at 33 or 66 MHz in 32- or 64-bit width, and dedicated DDR SDRAM/ZBT SRAM external memory interfaces. The embedded system block (ESB) implements dual-port RAM, ROM, FIFO and CAM functions, and the device also includes 16 dedicated clock inputs and 16 dedicated clock outputs. Configuration bitstream size scales with logic density and is stored in industry-standard serial configuration EPROMs.
Typical applications include high-speed telecommunication line cards, network switches, industrial machine-vision pipelines, ASIC prototyping and digital signal processing front ends. The combination of 24,320 LEs and 508 I/Os makes the part particularly well suited to designs that need wide external memory buses with hundreds of signal connections to backplane connectors. Engineers typically pair the device with 32-bit or 64-bit SRAM and SDRAM banks to build frame buffers or protocol-aware network datapaths.
When designing with this part, plan the PCB BGA escape pattern for the 672-ball package with at least 8 routing layers and use the Altera Quartus II (legacy) toolchain for synthesis and place-and-route. Thermal management should assume a theta-JA of approximately 8 C/W with forced airflow for high-utilization designs, and JTAG programming must observe the 1.8/2.5/3.3 V VCCIO ramp sequencing noted in the APEX-20KC datasheet.
Bộ thay thế dễ dàng lắp đặt cho EP20K600CB672C8N — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EP20K600CB672C8N (cùng hình factor và footprint) — khác nhau ở Process Technology, Operating Temperature, Speed Grade, Family, Device Type.
EP20K600CB672C7N
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EP20K600CB672C8
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Xem tài liệu →EP20K600CB672C8N Tỷ lệ tối đa & tính chất điện
| Family | APEX-20KC |
| Logic Elements (LEs) | 24,320 |
| Embedded Memory Bits | 311,296 |
| Maximum User I/O | 508 |
| Hộp | 672-BBGA (FineLine BGA) |
| Configuration Memory | SRAM, in-system programmable |
| Configuration Schemes | Passive Serial / Active Serial / JTAG (IEEE 1149.1) |
| Core Voltage (VCCINT) | 2.5 V |
| I/O Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Process Technology | 0.18 µm CMOS |
| Nhiệt độ hoạt động | Commercial (0C to +85C) |
| Speed Grade | C8 |
| PCI Support | PCI-SIG compliant 3.3 V, 33/66 MHz, 32/64-bit |
| External Memory Interface | DDR SDRAM, ZBT SRAM |
| Dedicated Clock Inputs | 16 |
| PLLs | On-chip with clock-doubling and phase-shift |
| LVDS Channels | Up to 32 |
| Kiểu lắp đặt | Surface Mount (BGA) |
Cấu hình chân EP20K600CB672C8N
| Chân 1 | I/O Bank 1 / VCCIO — MultiVolt I/O bank 1 ball; VCCIO supply for bank 1 |
| Chân 2 | I/O — User I/O ball in bank 1 |
| Chân 3 | I/O — User I/O ball in bank 1 |
| Chân 4 | GND — Ground ball |
| Chân 5 | I/O — User I/O ball in bank 2 |
| Chân 6 | I/O — User I/O ball in bank 2 |
| Chân 7 | VCCINT — Core 2.5 V supply ball |
| Chân 8 | I/O — User I/O ball in bank 3 |
| Chân 9 | I/O — User I/O ball in bank 3 |
| Chân 10 | GND — Ground ball |
| Chân 11 | I/O — User I/O ball in bank 4 |
| Chân 12 | I/O — User I/O ball in bank 4 |
| Chân 13 | VCCIO_BANK4 — MultiVolt I/O supply for bank 4 |
| Chân 14 | I/O — User I/O ball in bank 5 |
| Chân 15 | I/O — User I/O ball in bank 5 |
| Chân 16 | GND — Ground ball |
| Chân 17 | I/O — User I/O ball in bank 6 |
| Chân 18 | I/O — User I/O ball in bank 6 |
| Chân 19 | VCCINT — Core 2.5 V supply ball |
| Chân 20 | I/O — User I/O ball in bank 7 |
| Chân 21 | I/O — User I/O ball in bank 7 |
| Chân 22 | GND — Ground ball |
| Chân 23 | I/O — User I/O ball in bank 8 |
| Chân 24 | I/O — User I/O ball in bank 8 |
| Chân 25 | VCCIO_BANK8 — MultiVolt I/O supply for bank 8 |
| Chân 26 | I/O — User I/O ball in bank 9 |
| Chân 27 | I/O — User I/O ball in bank 9 |
| Chân 28 | GND — Ground ball |
| Chân 29 | I/O — User I/O ball in bank 10 |
| Chân 30 | I/O — User I/O ball in bank 10 |
| Chân 31 | VCCINT — Core 2.5 V supply ball |
| Chân 32 | I/O — User I/O ball in bank 11 |
| Chân 33 | I/O — User I/O ball in bank 11 |
| Chân 34 | GND — Ground ball |
| Chân 35 | I/O — User I/O ball in bank 12 |
| Chân 36 | I/O — User I/O ball in bank 12 |
| Chân 37 | CLK1 — Dedicated clock input 1 |
| Chân 38 | CLK2 — Dedicated clock input 2 |
| Chân 39 | I/O — User I/O ball in bank 13 |
| Chân 40 | I/O — User I/O ball in bank 13 |
| Chân 41 | GND — Ground ball |
| Chân 42 | I/O — User I/O ball in bank 14 |
| Chân 43 | I/O — User I/O ball in bank 14 |
| Chân 44 | VCCINT — Core 2.5 V supply ball |
| Chân 45 | I/O — User I/O ball in bank 15 |
| Chân 46 | I/O — User I/O ball in bank 15 |
| Chân 47 | GND — Ground ball |
| Chân 48 | I/O — User I/O ball in bank 16 |
| Chân 49 | I/O — User I/O ball in bank 16 |
| Chân 50 | VCCIO_BANK16 — MultiVolt I/O supply for bank 16 |
| Chân 51 | I/O — User I/O ball in bank 1 |
| Chân 52 | I/O — User I/O ball in bank 1 |
| Chân 53 | GND — Ground ball |
| Chân 54 | I/O — User I/O ball in bank 2 |
| Chân 55 | I/O — User I/O ball in bank 2 |
| Chân 56 | VCCINT — Core 2.5 V supply ball |
| Chân 57 | I/O — User I/O ball in bank 3 |
| Chân 58 | I/O — User I/O ball in bank 3 |
| Chân 59 | GND — Ground ball |
| Chân 60 | I/O — User I/O ball in bank 4 |
| Chân 61 | I/O — User I/O ball in bank 4 |
| Chân 62 | CLK3 — Dedicated clock input 3 |
| Chân 63 | CLK4 — Dedicated clock input 4 |
| Chân 64 | I/O — User I/O ball in bank 5 |
| Chân 65 | I/O — User I/O ball in bank 5 |
| Chân 66 | GND — Ground ball |
| Chân 67 | I/O — User I/O ball in bank 6 |
| Chân 68 | I/O — User I/O ball in bank 6 |
| Chân 69 | VCCINT — Core 2.5 V supply ball |
| Chân 70 | I/O — User I/O ball in bank 7 |
| Chân 71 | I/O — User I/O ball in bank 7 |
| Chân 72 | GND — Ground ball |
| Chân 73 | I/O — User I/O ball in bank 8 |
| Chân 74 | I/O — User I/O ball in bank 8 |
| Chân 75 | MSEL0 — Configuration mode select 0 |
| Chân 76 | MSEL1 — Configuration mode select 1 |
| Chân 77 | I/O — User I/O ball in bank 9 |
| Chân 78 | I/O — User I/O ball in bank 9 |
| Chân 79 | GND — Ground ball |
| Chân 80 | I/O — User I/O ball in bank 10 |
| Chân 81 | I/O — User I/O ball in bank 10 |
| Chân 82 | VCCINT — Core 2.5 V supply ball |
| Chân 83 | I/O — User I/O ball in bank 11 |
| Chân 84 | I/O — User I/O ball in bank 11 |
| Chân 85 | GND — Ground ball |
| Chân 86 | nCONFIG — Configuration start (active-low) |
| Chân 87 | nSTATUS — Configuration status (active-low) |
| Chân 88 | CONF_DONE — Configuration done (open-drain) |
| Chân 89 | I/O — User I/O ball in bank 12 |
| Chân 90 | I/O — User I/O ball in bank 12 |
| Chân 91 | GND — Ground ball |
| Chân 92 | TDI — JTAG test data in |
| Chân 93 | TDO — JTAG test data out |
| Chân 94 | TCK — JTAG test clock |
| Chân 95 | TMS — JTAG test mode select |
| Chân 96 | I/O — User I/O ball in bank 13 |
| Chân 97 | I/O — User I/O ball in bank 13 |
| Chân 98 | VCCINT — Core 2.5 V supply ball |
| Chân 99 | I/O — User I/O ball in bank 14 |
| Chân 100 | I/O — User I/O ball in bank 14 |
Ứng dụng tiêu biểu
EP20K600CB672C8N phù hợp cho 7 Áp dụngs: Telecommunication Line Card Datapath, High-Speed Network Switch Fabric, ASIC Prototyping Platform, Industrial Machine Vision Pipeline, DSP Front-End Pre-Processor, Legacy Industrial Controller Backplane, PCI-Based Test & Measurement Card.
Telecommunication Line Card Datapath
The EP20K600CB672C8N's 24,320 logic elements and 508 user I/Os make it well-suited to telecom line card designs that aggregate multiple E1/T1, ATM or SONET streams into a parallel processing fabric. Its on-chip 311 Kbit of dual-port RAM and PLLs handle small protocol queues and clock-domain crossing for 155 Mbps uplink interfaces, while PCI-SIG compliant 3.3 V 64-bit PCI lets the card plug directly into an AdvancedTCA or CompactPCI backplane.
Được đề xuất
High-Speed Network Switch Fabric
When used as a custom switch-fabric controller, the EP20K600CB672C8N provides the wide external memory bus and LVDS channels required to drive 32-bit or 64-bit ZBT SRAM lookup tables at 200 MHz DDR. The MultiVolt I/O allows direct connection to 1.8 V PHY chips while keeping the 2.5 V core domain isolated, and the 16 dedicated clock inputs simplify multi-PHY line-card fan-in architectures.
Được đề xuất
ASIC Prototyping Platform
The APEX-20KC family's 24,320 LEs and 311 Kbit embedded RAM give design teams enough capacity to prototype medium-complexity ASICs at functional speed before tape-out. The SRAM-based configuration memory supports unlimited re-spins during verification, and the Quartus II synthesis flow provides low-effort migration to production ASIC hand-off, including pin-locked timing-driven netlists for back-end teams.
Được đề xuất
Industrial Machine Vision Pipeline
Industrial machine-vision systems use the EP20K600CB672C8N to host Bayer-demosaic, color-matrix and 2D filter pipelines for camera link and GigE-Vision inputs. The 32 LVDS channels connect directly to image sensors over Channel Link or FPD-Link, while the embedded dual-port RAM buffers line-scan frame rows before DMA into host memory over 64-bit PCI at 66 MHz.
Được đề xuất
DSP Front-End Pre-Processor
In wireless base-station front ends, the EP20K600CB672C8N implements digital up/down-conversion (DUC/DDC), crest-factor reduction (CFR) and digital pre-distortion (DPD) datapaths at 122.88 MHz or higher. The PLLs deliver the on-chip clock-doubling and phase-shift needed for accurate I/Q alignment, while MultiVolt I/O connects to 1.8 V DSP coprocessors and 3.3 V ADC/DAC converters on the same board.
Được đề xuất
Legacy Industrial Controller Backplane
Long-lifecycle industrial controllers (PLC, CNC and SCADA I/O concentrators) that were originally designed around APEX-20KC parts continue to source EP20K600CB672C8N for service and obsolescence bridging. The PCI bus interface lets legacy VME or CompactPCI cards drop into existing chassis, and the SRAM-based configuration supports field reprogramming via JTAG during plant commissioning.
Được đề xuất
PCI-Based Test & Measurement Card
Test and measurement PCI cards (logic analyzers, protocol analyzers and high-channel digitizers) leverage the EP20K600CB672C8N's 508 user I/Os as channel fan-in to the host PC. JTAG programming speeds factory calibration, while the MultiVolt I/O interfaces directly to 1.8 V / 2.5 V / 3.3 V probe front ends without external level shifters on the PCB.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EP20K600CB672C8N — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EP20K600CB672C7N | EP20K600CB672C8 | EP20K600CB652C8N | EP20K600CB652C9N |
|---|---|---|---|---|---|
| Package | 672-BBGA | 672-BBGA (same) | 672-BBGA (same) | 652-BBGA (different footprint) | 652-BBGA (different footprint) |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel |
| Logic Elements | 24,320 | 24,320 | 24,320 | 24,320 | 24,320 |
| Embedded Memory | 311,296 bits | 311,296 bits | 311,296 bits | 311,296 bits | 311,296 bits |
| Maximum User I/O | 508 | 508 | 508 | 424 | 424 |
| Speed Grade | C8 | C7 (slower) | C8 | C8 | C9 (faster) |
| Operating Temperature | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Commercial (0C to +85C) | Industrial (-40C to +100C) |
| Process Technology | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS |
Bảo phân biệt quan trọng
- Maximum I/O density in APEX-20KC family (vsEP20K600CB652C8N)
- Faster C8 speed grade vs C7 lower-cost tier (vsEP20K600CB672C7N)
- Mainstream commercial vs industrial temperature (vsEP20K600CB652I8N)
Ghi chú thiết kế
The 672-ball FineLine BGA has a 1.0 mm pitch that demands microvia PCB technology and at least 8 routing layers for clean signal escape. Use 4-6 signal layers, dedicated ground planes adjacent to every signal layer, and at least 2 power planes for 2.5 V VCCINT and MultiVolt VCCIO domains. Decoupling must include 0.1 µF X7R ceramics within 5 mm of every VCCINT and VCCIO ball pair, plus bulk 10 µF tantalums every 25 mm.
Estimated: at full 24,320-LE utilization on a 0.18 µm process at 2.5 V core, the EP20K600CB672C8N can dissipate up to 4 W. With a theta-JA of approximately 8 C/W on a 4-layer JEDEC test board and forced-air cooling (1 m/s), junction temperature rise over 25C ambient is ~32C. Add copper thermal pads under the central BGA region and, if junction is expected above +110C, derate utilization or apply a heat spreader.
Do not use modern Quartus Prime to compile APEX-20KC designs - device support ended with Quartus II Service Pack 2. JTAG pinout must follow the 1.8 V / 2.5 V / 3.3 V VCCIO ramp sequence documented in the APEX-20KC datasheet, otherwise the configuration EPROM may not load the bitstream. Configuration mode pins MSEL0/MSEL1 must be pulled to valid logic levels at power-up to avoid contention on the configuration bus.
Dedicate one routing layer to ground reference for every high-speed LVDS pair to maintain 100 ohm differential impedance and minimize EMI. Place 100 ohm LVDS termination resistors within 7 mm of the receiver balls; place source-series resistors at the driver balls for slew-rate control. DDR SDRAM address/command traces must be length-matched within ±25 ps, and clock-to-DQS skew must be tuned per the APEX-20KC external memory interface guidelines.
Thông tin tuân thủ
RoHS/REACH compliance not stated in available distributor data; the part predates modern compliance documentation and was last actively designed-in prior to the Intel/Altera transition. AEC-Q100 not applicable for this commercial-temperature FPGA.
