EP910PC-0 - Classic EPLD, 24 Macrocells, 40-Pin PDIP | Altera
MPN: EP910PC-0 ✗ Cuối đờiEP910PC-0 Tóm tắt
An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that combines multiple PAL/GAL-style AND/OR arrays with a shared programmable interconnect and a fixed OR array of macrocells. EPLDs sit in the taxonomy below modern CPLDs and FPGAs: programmable logic -> CPLD/EPLD -> PAL/GAL replacement -> logic integration IC. The Classic EPLD family was Altera's flagship low-density glue-logic replacement family in the late 1980s and 1990s, offering 100% TTL-compatible I/O and in-system erasability via a quartz window or, for plastic packages, one-time-programmable (OTP) UV-erasable silicon.
Key features of the EP910PC-0 include 24 macrocells, 10 dedicated input pins, 24 I/O pins, a maximum propagation delay in the slowest ("-0") speed grade, 5V single-supply operation, and TTL-compatible logic thresholds. The device is implemented in CMOS technology for low power consumption, with each macrocell containing a programmable AND/OR array and a flip-flop. The Classic EPLD macrocell architecture enables pin-to-pin replacement of multiple 20- and 24-pin PAL/GAL devices, dramatically reducing board area and part count in legacy logic designs.
Typical applications include TTL glue-logic replacement, bus-interface decoding, state-machine implementation, address decoding for microprocessor systems, and consolidation of multiple PAL/GAL devices in industrial control, telecommunications, and military/aerospace systems. The PDIP-40 through-hole package is favored for prototype development, breadboarding, and legacy systems where socketed parts simplify field serviceability. When designing with the EP910PC-0, engineers should note that the "-0" speed grade is the slowest available; for time-critical paths, the "-15", "-20", "-25", "-30", or "-35" grades provide progressively faster propagation delays in the same PDIP-40 footprint. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes for engineers maintaining or replicating legacy Altera Classic EPLD designs.
Bộ thay thế dễ dàng lắp đặt cho EP910PC-0 — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với EP910PC-0 (cùng hình factor và footprint) — khác nhau ở Package, Programming Method, Usable Gates, Supply Voltage (VCC), Technology.
EP910PC-30
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910PC-35
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910IPC-25
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910PI-35
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910DC-30
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →EP910PC-20
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →EP910PC-0 Tỷ lệ tối đa & tính chất điện
| Product Type | EPLD (Erasable Programmable Logic Device) |
| Family | Classic EPLD |
| Usable Gates | 900 gates |
| Macrocells | 24 |
| Logic Blocks | 6 (4 macrocells each) |
| Dedicated Inputs | 10 |
| I/O Pins | 24 |
| Hộp | PDIP-40 (Plastic DIP, 40-pin) |
| Speed Grade | -0 (slowest) |
| Điện áp cung cấp | 5 V (single supply) |
| Process Technology | CMOS |
| Logic Compatibility | 100% TTL emulation |
| Nhiệt độ hoạt động | 0C to +70C (commercial) |
| Programming Method | UV-erasable / OTP |
| Kiểu lắp đặt | Through-Hole (DIP) |
Cấu hình chân EP910PC-0
| Chân 1 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 2 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 3 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 4 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 5 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 6 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 7 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 8 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 9 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 10 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 11 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 12 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 13 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 14 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 15 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 16 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 17 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 18 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 19 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 20 | GND — Ground (0V) |
| Chân 21 | INPUT — Dedicated input pin |
| Chân 22 | INPUT — Dedicated input pin |
| Chân 23 | INPUT — Dedicated input pin |
| Chân 24 | INPUT — Dedicated input pin |
| Chân 25 | INPUT — Dedicated input pin |
| Chân 26 | INPUT — Dedicated input pin |
| Chân 27 | INPUT — Dedicated input pin |
| Chân 28 | INPUT — Dedicated input pin |
| Chân 29 | INPUT — Dedicated input pin |
| Chân 30 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 31 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 32 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 33 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 34 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 35 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 36 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 37 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 38 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 39 | I/O — Bidirectional I/O pin (macrocell controlled) |
| Chân 40 | VCC — 5V supply voltage |
Ứng dụng tiêu biểu
EP910PC-0 phù hợp cho 6 Áp dụngs: TTL Glue Logic Replacement, Microprocessor Bus Address Decoding, State Machine Implementation, Legacy Industrial Control Systems, Telecommunications Interface Logic, Avionics and Military Logic Replacement.
TTL Glue Logic Replacement
The EP910PC-0's 24 macrocells and 100% TTL-compatible I/O make it ideal for replacing networks of 74-series TTL gates and 20-/24-pin PAL/GAL devices in legacy logic designs. With 900 usable gates and 24 bidirectional I/O pins, a single EP910PC-0 can consolidate 4-8 standard PALs, reducing board area, power consumption, and part count. Engineers typically use it for address decoding, control-signal generation, and bus arbitration in microprocessor-based systems where socketed PDIP parts simplify field serviceability. The OTP (one-time-programmable) plastic package is favored for production runs once the design is finalized and verified.
Được đề xuất
Microprocessor Bus Address Decoding
The EP910PC-0's 24 macrocells provide ample capacity for full 16-/20-bit address decoding in 8086, 68000, and Z80 microprocessor systems, replacing 3-5 dedicated PALs. Its 10 dedicated inputs accommodate full address-bus plus chip-select and read/write control inputs, while the 24 I/O pins drive chip-select, buffer-enable, and interrupt-control signals. The CMOS technology and 5V single-supply operation ensure compatibility with vintage TTL logic. Designers appreciate the PDIP-40 package for prototype breadboards and the OTP plastic variant for cost-sensitive production.
Được đề xuất
State Machine Implementation
Each EP910PC-0 macrocell contains a programmable flip-flop (D, T, JK, or SR), making the device well-suited to state-machine controllers with 8-16 states. The 24 macrocells support multiple concurrent state machines (e.g., a 6-state main controller plus a 4-state peripheral controller) within a single chip. The Classic EPLD macrocell architecture provides deterministic timing ideal for synchronous control logic in industrial automation, instrumentation, and telecommunications equipment. The PDIP-40 footprint allows easy insertion into through-hole prototype boards during state-machine debugging.
Được đề xuất
Legacy Industrial Control Systems
Many long-lifecycle industrial systems (PLC I/O modules, motor controllers, CNC interfaces) designed in the 1990s use the EP910PC-0 for control-logic integration. The Classic EPLD's CMOS low-power operation, 5V supply, and proven reliability over decades make it a mainstay for maintenance and refurbishment of legacy equipment. The PDIP-40 through-hole package accommodates the wave-soldering and socket-replacement workflows common in industrial field service. As of 2026-09-10, secondary-market distributors maintain limited stock to support these installed-base applications.
Được đề xuất
Telecommunications Interface Logic
The EP910PC-0's 24 macrocells and TTL-compatible I/O suit telecommunications interface designs requiring custom framing, line-coding, and protocol-conversion logic. Engineers used the EP910 family for HDLC/SDLC controllers, RS-232/RS-422 line-interface glue logic, and T1/E1 framing circuits in 1990s telecom equipment. Its deterministic propagation delay and CMOS noise immunity are advantageous for low-speed serial-control paths. The PDIP-40 package remains valuable for prototype development of telecom-interface daughter cards.
Được đề xuất
Avionics and Military Logic Replacement
Military and avionics programs adopted the EP910 family in the 1990s for radar signal conditioning, navigation-computer glue logic, and weapons-system controllers requiring radiation-tolerant CMOS EPLDs. Although modern programs have migrated to radiation-hard FPGAs, the EP910PC-0 still appears in legacy system sustainment programs. The ceramic-DIP variants (EP910DC-NN) are preferred for high-reliability applications. Note that the EP910PC-0 plastic version is commercial-grade and NOT suitable for new military designs.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho EP910PC-0 — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | EP910PC-30 | EP910PC-35 | EP910IPC-25 | EP910PI-35 | EP910DC-30 | EP910PC-20 |
|---|---|---|---|---|---|---|---|
| Package | PDIP-40 (Plastic DIP) | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 - same | PDIP-40 (Ceramic) - same footprint | PDIP-40 - same |
| Brand | Altera | Altera - same brand | Altera - same brand | Altera - same brand | Altera - same brand | Altera - same brand | Altera - same brand |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 | 24 |
| Usable Gates | 900 | 900 | 900 | 900 | 900 | 900 | 900 |
| Speed Grade (tPD) | -0 (~75 ns, slowest) | -30 (33 ns) - faster | -35 (30 ns) - faster | -25 (45 ns) - faster | -35 (35 ns) - faster | -30 (33 ns) - faster | -20 (50 ns) - faster |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial, ceramic) | 0C to +70C (Commercial) |
| Package Material | Plastic (OTP) | Plastic (OTP) | Plastic (OTP) | Plastic (OTP) | Plastic (OTP) | Ceramic (UV-erasable) | Plastic (OTP) |
| Logic Compatibility | 100% TTL | 100% TTL | 100% TTL | 100% TTL | 100% TTL | 100% TTL | 100% TTL |
Bảo phân biệt quan trọng
- Original slowest speed grade of EP910 family (vsEP910PC-30)
- Lowest-density member still in active legacy use (vsEP910PC-30 / EP910PC-35)
- Plastic PDIP package enables OTP cost savings (vsEP910DC-30 (ceramic DIP))
Ghi chú thiết kế
The EP910PC-0 plastic package is one-time-programmable (OTP) - there is no UV-erase window. Design bugs are PERMANENT once programmed. Engineers MUST prototype using a windowed ceramic-DIP variant (EP910DC-30) for development and verification, then move to the EP910PC-0 for cost-optimized production. Always retain a working ceramic-DIP unit programmed with the latest design revision. Programming files (JEDEC format) should be archived with revision history because re-spinning the EP910PC-0 is impossible.
Estimated: with tPD = 75 ns and TTL-compatible I/O, the EP910PC-0 cannot drive signals faster than ~13 MHz reliably. For designs requiring bus frequencies above 10 MHz, use a faster grade (EP910PC-30 at 33 ns) or move to a modern CPLD like MAX V. Unused I/O pins MUST be configured as outputs and tied to ground (or left as inputs with internal pull-up enabled in the JEDEC fuse map) - floating unused inputs can cause supply-current spikes and logic oscillation on TTL-compatible CMOS EPLDs.
The EP910PC-0 PDIP-40 package requires 0.1uF decoupling capacitors on VCC (pin 40) placed within 5mm of the supply pin. The classic Altera EPLD datasheet recommends one bulk 10uF tantalum capacitor and one 0.1uF ceramic per device. Ground (pin 20) MUST be connected to a low-impedance ground plane - the EP910 family uses pin 20 as the sole GND, and inadequate grounding causes I/O timing skew and macrocell metastability. Socket the device in production boards to allow replacement.
Thông tin tuân thủ
EP910PC-0 is an obsolete Altera (now Intel) Classic EPLD from the 1990s. RoHS/REACH compliance status is not documented in current distributor listings because the part was designed before RoHS directives; lead-free status is unknown. Not AEC-Q100 qualified. Engineers requiring compliance should source from authorized obsolete-stock distributors who can provide compliance documentation per lot.
