LTC2291IUP - Dual 12-Bit 25Msps Low-Power 3V ADC | Analog Devices
MPN: LTC2291IUP ✓ Hoạt độngLTC2291IUP Tóm tắt
An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that samples a continuous analog input voltage and produces a discrete digital code proportional to that input. Pipeline ADCs in particular use a multi-stage architecture with per-stage flash sub-ADCs and DACs to achieve high sample rates (tens to hundreds of Msps) at moderate resolution (10-14 bits) while keeping power dissipation low - they sit in the converter hierarchy between flash (highest speed, lowest resolution) and sigma-delta (highest resolution, lowest speed). The dual-channel LTC2291 occupies the lower-power end of the 25 Msps class, drawing roughly 1.5W per channel.
Key features of the LTC2291IUP include 71.3 dB SNR and 90 dB SFDR at the Nyquist input frequency, differential input architecture for excellent common-mode noise rejection, selectable input ranges of ±1V or ±0.5V around a common-mode level near 2V, and a flexible LVDS/CMOS output interface. The device operates from a single 2.85V-3.3V analog supply, includes an internal reference, and offers an optional external reference mode for gain accuracy.
Typical applications for the LTC2291 include communications receivers (cellular base-station I/Q digitizers), medical imaging (ultrasound beamforming front-ends), high-end instrumentation (digital oscilloscopes and spectrum analyzers), and defense/multimedia systems. The combination of low power and dual-channel density also makes it a frequent choice for handheld test equipment.
When designing with this part, pay special attention to analog input common-mode biasing and decoupling - the LTC2291 requires AC-coupling or DC bias networks on each input, and ground-bounce on the analog supply can couple directly into the sample clock jitter.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Bộ thay thế dễ dàng lắp đặt cho LTC2291IUP — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với LTC2291IUP (cùng hình factor và footprint) — khác nhau ở Package, SFDR, SNR, Input Type, RoHS Status.
LTC2290IUP
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2292IUP
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2293IUP
✅ Drop-In ⚠️ Thông số chưa được xác minh📋 Tham chiếu thay thế (không có trong danh mục)
LTC2289IUP
✅ Drop-In ⚠️ Thông số chưa được xác minh📋 Tham chiếu thay thế (không có trong danh mục)
LTC2283IUP
✅ Drop-In📋 Tham chiếu thay thế (không có trong danh mục)
LTC2241IUP-12
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →LTC2291IUP Tỷ lệ tối đa & tính chất điện
| Độ phân giải | 12 bit |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sample Rate | 25 Msps |
| Architecture | Pipelined |
| Input Type | Differential |
| Analog Supply Voltage | 2.85 V to 3.3 V (single 3 V) |
| Digital Supply Voltage | 2.85 V to 3.3 V |
| Phạm vi điện áp đầu vào | ±1 V or ±0.5 V (selectable) |
| SNR | 71.3 dB at Nyquist input |
| SFDR | 90 dB at Nyquist input |
| Output Interface | CMOS / LVDS (selectable) |
| Hộp | 64-pin QFN (9 mm x 9 mm) |
| Nhiệt độ hoạt động | -40 C to +85 C (industrial) |
| Kiểu lắp đặt | Surface Mount |
| Trạng thái RoHS | Compliant |
Cấu hình chân LTC2291IUP
| Chân 1 | DGND — Digital ground |
| Chân 2 | OVCC — Output driver supply |
| Chân 3 | VREF — Reference voltage decoupling |
| Chân 4 | MODE — Mode configuration |
| Chân 5 | SENSE — Input range select |
| Chân 6 | VCM — Common-mode voltage output |
| Chân 7 | NC — Not connected |
| Chân 8 | AIN1+ — Channel 1 differential input positive |
| Chân 9 | AIN1- — Channel 1 differential input negative |
| Chân 10 | AGND — Analog ground |
| Chân 11 | AVCC — Analog supply |
| Chân 12 | NC — Not connected |
| Chân 13 | AIN2+ — Channel 2 differential input positive |
| Chân 14 | AIN2- — Channel 2 differential input negative |
| Chân 15 | AGND — Analog ground |
| Chân 16 | AVCC — Analog supply |
| Chân 17 | CLK+ — Differential clock positive |
| Chân 18 | CLK- — Differential clock negative |
| Chân 19 | NC — Not connected |
| Chân 20 | DGAIN — Digital gain adjustment |
| Chân 21 | D11A — Channel 1 data bit 11 (MSB) |
| Chân 22 | D10A — Channel 1 data bit 10 |
| Chân 23 | D9A — Channel 1 data bit 9 |
| Chân 24 | D8A — Channel 1 data bit 8 |
| Chân 25 | D7A — Channel 1 data bit 7 |
| Chân 26 | D6A — Channel 1 data bit 6 |
| Chân 27 | D5A — Channel 1 data bit 5 |
| Chân 28 | D4A — Channel 1 data bit 4 |
| Chân 29 | D3A — Channel 1 data bit 3 |
| Chân 30 | D2A — Channel 1 data bit 2 |
| Chân 31 | D1A — Channel 1 data bit 1 |
| Chân 32 | D0A — Channel 1 data bit 0 (LSB) |
| Chân 33 | DGND — Digital ground |
| Chân 34 | OVCC — Output driver supply |
| Chân 35 | OF — Output data flag |
| Chân 36 | OGND — Output ground |
| Chân 37 | OVCC — Output driver supply |
| Chân 38 | D0B — Channel 2 data bit 0 (LSB) |
| Chân 39 | D1B — Channel 2 data bit 1 |
| Chân 40 | D2B — Channel 2 data bit 2 |
| Chân 41 | D3B — Channel 2 data bit 3 |
| Chân 42 | D4B — Channel 2 data bit 4 |
| Chân 43 | D5B — Channel 2 data bit 5 |
| Chân 44 | D6B — Channel 2 data bit 6 |
| Chân 45 | D7B — Channel 2 data bit 7 |
| Chân 46 | D8B — Channel 2 data bit 8 |
| Chân 47 | D9B — Channel 2 data bit 9 |
| Chân 48 | D10B — Channel 2 data bit 10 |
| Chân 49 | D11B — Channel 2 data bit 11 (MSB) |
| Chân 50 | NC — Not connected |
| Chân 51 | DGND — Digital ground |
| Chân 52 | ENC — Encode clock out / sync |
| Chân 53 | OF — Output data flag |
| Chân 54 | NC — Not connected |
| Chân 55 | OGND — Output ground |
| Chân 56 | OVCC — Output driver supply |
| Chân 57 | NC — Not connected |
| Chân 58 | NC — Not connected |
| Chân 59 | AGND — Analog ground |
| Chân 60 | AVCC — Analog supply |
| Chân 61 | NC — Not connected |
| Chân 62 | NC — Not connected |
| Chân 63 | NC — Not connected |
| Chân 64 | DGND — Digital ground |
Ứng dụng tiêu biểu
LTC2291IUP phù hợp cho 6 Áp dụngs: Communications Receiver IF Digitizer, Medical Ultrasound Beamforming, Handheld Digital Oscilloscope Front-End, WCDMA Diversity Receiver, Multichannel Industrial Data Acquisition, Portable Imaging / Video Digitizer.
Communications Receiver IF Digitizer
The LTC2291IUP is well suited for digitizing intermediate-frequency (IF) signals in cellular base-station receivers and software-defined radio (SDR) front-ends. Its dual-channel architecture handles I/Q signal pairs simultaneously, capturing in-phase and quadrature components of a single IF channel without time skew - critical for demodulation accuracy. The 71.3 dB SNR and 90 dB SFDR at the Nyquist frequency let designers place the ADC close to the mixer output, eliminating a downconversion stage. Operated from a single 3 V supply and clocked at 25 Msps, the part draws very low power per channel compared to 14-bit alternatives, easing thermal design in outdoor radio units. Recommended companions: LF353 op-amp, AD8138 differential driver.
Được đề xuất
Medical Ultrasound Beamforming
In phased-array ultrasound systems, each piezoelectric element requires a dedicated ADC channel running at 20-40 Msps with 12-bit dynamic range - the LTC2291IUP's dual-channel density integrates two such channels on one die, simplifying beamformer PCB layout. The 71.3 dB SNR preserves the 60 dB+ dynamic range required to resolve tissue echoes, while the differential inputs reject common-mode noise from adjacent switching high-voltage transmit pulsers. The exposed thermal pad and 9x9 mm QFN package spread heat evenly, allowing 32+ channel systems to fit on a single beamformer board. Recommended companions: AD8021 op-amp, DAC8564 transmit waveform DAC.
Được đề xuất
Handheld Digital Oscilloscope Front-End
Portable oscilloscopes need to digitize 20-100 MHz analog bandwidth at sample rates up to 1 Gsps, typically by interleaving multiple 25 Msps ADCs. The LTC2291IUP operates as one element in a 4-way or 8-way time-interleaved front-end, where each dual channel captures alternating sample slots. Its low power dissipation preserves battery runtime, while the LVDS output mode minimizes digital switching noise that would otherwise alias into the analog input path. Front-panel oscilloscope designers value the industrial temperature grade and lead-free QFN footprint. Recommended companions: CDCE906 clock generator, SN65LVDS31 serializers.
Được đề xuất
WCDMA Diversity Receiver
Diversity receivers in WCDMA/LTE base stations capture two simultaneous antenna signals and combine them via MRC (Maximal Ratio Combining) to improve fade margin. The LTC2291IUP's two identical channels, sampled by a shared clock, are perfectly aligned in time so combining coefficients can be applied without skew correction. The 71.3 dB SNR guarantees the 60+ dB signal-to-noise ratio required for high-order modulation decoding, and the 25 Msps rate comfortably exceeds the 3.84 Mcps chip rate after decimation filtering. Differential inputs reject common-mode pickup in dense antenna arrays. Recommended companions: ADL5501 RSSI detector, FPGA-based baseband processor.
Được đề xuất
Multichannel Industrial Data Acquisition
Industrial DAQ systems monitor multiple analog sensors (temperature, pressure, vibration, strain gauges) and require simultaneous sampling to preserve phase relationships. The LTC2291IUP's dual-channel sampling makes it economical for channel counts in the 16-64 range; four LTC2291IUPs deliver 8 channels per PCB row with a single shared clock tree. The industrial -40 C to +85 C temperature grade handles factory environments, and the wide-input ±1 V range accommodates industrial transducer outputs directly with minimal signal conditioning. Anti-alias filtering is straightforward at the 12.5 MHz Nyquist band. Recommended companions: AD8230 instrumentation amp, ISO124 isolation amp.
Được đề xuất
Portable Imaging / Video Digitizer
Industrial cameras and handheld video inspection tools digitize composite or component video at rates around 14-30 Msps per channel - exactly the operating envelope of the LTC2291IUP. The dual channels can digitize Y/C (luminance/chrominance) simultaneously, or two RGB component streams for color-inspection imaging. Low per-channel power keeps the imaging probe thermally cool against the user's hand or plastic enclosure, while the small 9x9 mm QFN footprint preserves compact camera head designs. Differential inputs reject ground-bounce between probe and main unit. Recommended companions: EL4081 sync separator, FPGA image processor.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho LTC2291IUP — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | LTC2290IUP | LTC2292IUP | LTC2293IUP | LTC2289IUP | LTC2283IUP |
|---|---|---|---|---|---|---|
| Package | 64-pin QFN (9x9) | 64-pin QFN (9x9) - same | 64-pin QFN (9x9) - same | 64-pin QFN (9x9) - same | 64-pin QFN (9x9) - same | 64-pin QFN (9x9) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 10 bit | 12 bit |
| Sample Rate | 25 Msps | 10 Msps | 40 Msps | 65 Msps | 25 Msps | 25 Msps |
| Number of Channels | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) | 2 (dual) |
| Input Type | Differential | Differential | Differential | Differential | Differential | Differential |
| Output Interface | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS | CMOS / LVDS |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| RoHS Status | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Bảo phân biệt quan trọng
- Lowest sample rate in LTC2293 family gives lowest power (vsLTC2292IUP)
- Higher resolution than 10-bit dual ADCs (vsLTC2289IUP)
- Same footprint as higher-speed LTC2293 (vsLTC2293IUP)
Ghi chú thiết kế
Place the analog input traces symmetrically and as close to the ADC inputs as possible - the LTC2291IUP uses differential inputs and any length mismatch between AIN+ and AIN- paths will unbalance common-mode rejection. Shield the analog input traces with a ground plane on the next layer, and route the 25 MHz clock traces perpendicular to inputs to minimize crosstalk. The exposed thermal pad must be soldered to a continuous ground plane with at least 9 thermal vias for heat spreading.
Decouple AVCC and OVCC separately with 0.1 uF ceramic capacitors placed within 2 mm of each supply pin, plus a 10 uF bulk capacitor near the part. The analog and digital grounds should be joined at a single point under the IC exposed pad, not split across the entire PCB - a split ground at this ADC's frequency would inject switching noise into the analog front-end and degrade SNR by several dB.
Estimated: To preserve the full 71.3 dB SNR, the external clock source should have aperture jitter below 0.3 ps-rms. A typical crystal oscillator like the MXT555 at 25 MHz provides ~1 ps jitter which would limit SNR to around 68 dB - upgrade to a SAW oscillator or clock conditioner (e.g. AD9513 or LMX2531) when SNR-critical.
Do not operate the LTC2291IUP with DC-coupled single-ended inputs without biasing the common-mode level - the inputs are fully differential and the input pair will saturate without bias. Use AC coupling or include a resistive divider on each AIN+ and AIN- pin to set the common-mode voltage near the VCM output. Also ensure the SENSE pin is connected to AVDD or GND per datasheet - leave it floating causes undefined input range.
Thông tin tuân thủ
RoHS-compliant and lead-free per distributor listings. Halogen-free and conflict-mineral status not explicitly stated in the verified data; refer to the manufacturer's materials declaration for confirmation.
