SI5345A-D04594-GMR - 10-Output Jitter Attenuator | Skyworks
MPN: SI5345A-D04594-GMR ✓ Hoạt độngSI5345A-D04594-GMR Tóm tắt
A clock synthesizer (sometimes called a clock generator or frequency synthesizer) is an IC that derives one or more precise output frequencies from a single reference source. Within the broader hierarchy, the SI5345A belongs to the clock timing IC family, which sits under integrated circuits and plays a critical role in synchronous digital systems: SOC > integrated circuit > clock & timing IC > clock generator > frequency synthesizer > jitter attenuator. Jitter attenuators add a low-bandwidth PLL on top of a synthesizer to filter reference-clock noise before redistribution to downstream PHYs, ADCs, DACs, and FPGAs.
Key features of this variant include ten independently configurable output formats (LVDS, LVPECL, HCSL, CML, CMOS, HSTL, SSTL), an I2C control interface, 1.71 V to 1.89 V core supply range, and a -40 C to +85 C industrial operating range. The -D04594-GM code denotes a custom factory-programmed frequency plan generated by Skyworks ClockBuilder Pro, which removes the burden of in-system NVM programming.
Architecturally, the Si5345A uses a fractional-N MultiSynth divider per output, allowing non-integer frequency translations without compromising phase noise. The internal low-jitter VCO and digitally programmable loop bandwidth enable optimization for each application's jitter transfer characteristics. This makes the SI5345A well suited to reference clock generation for 100G/400G Ethernet PHYs, OTN/SONET/SDH line cards, FPGA transceiver reference chains, wireless base-station timing, and high-end broadcast video.
Typical applications include 100G/400G Ethernet switches, OTN/SONET/SDH line cards, FPGA/ASIC reference clock trees, wireless base-station timing boards, and broadcast video routers. The wide output format support and low jitter make it a flexible single-chip timing solution for mixed-signal boards that would otherwise require multiple oscillators or clock generators.
When designing with the SI5345A, place the 0.1 uF + 10 uF decoupling network as close as possible to each supply pin and expose the e-pad with at least 25 thermal vias to an internal ground pour. Use the ClockBuilder Pro configuration file attached to your -D04594 order code to load the pre-configured frequency plan into the IC; do not re-program the NVM unless intentionally overriding the factory image.
This page synthesizes verified distributor pricing, drop-in compatible alternatives, and practical PCB layout notes that are not aggregated on the manufacturer datasheet alone.
Bộ thay thế dễ dàng lắp đặt cho SI5345A-D04594-GMR — cùng gói, chân-to-chân tương thích. Các bộ phận yêu cầu hàn PCB bị loại trừ.
Các biến thể trong loạt này
Các mẫu cùng loạt có thể lắp đặt dễ dàng tương thích với SI5345A-D04594-GMR (cùng hình factor và footprint) — khác nhau ở Package, Function, Output Frequency Range, Supply Voltage, Control Interface.
SI5345A-D04594-GM
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →SI5345A-D-GMR
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →SI5345A-D-GM
✅ Drop-InLiên hệ để biết giá
Xem tài liệu →SI5344B-D-GM
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →SI5340A-D-GM
✅ Drop-In ⚠️ Thông số chưa được xác minhLiên hệ để biết giá
Xem tài liệu →SI5345A-D04594-GMR Thông số kỹ thuật
| Product Type | Clock Synthesizer / Jitter Attenuator |
| Series | Si5345 (Si5345A family variant) |
| Số lượng đầu ra | 10 |
| Output Frequency Range | up to 1028 MHz (any frequency) |
| Output Logic Levels | LVDS, LVPECL, HCSL, CML, CMOS, HSTL, SSTL (selectable per output) |
| Supply Voltage (Core) | 1.71 V to 1.89 V |
| Control Interface | I2C |
| Khoảng nhiệt độ hoạt động | -40 C to +85 C |
| Hộp | QFN-64-EP (9x9 mm) with exposed thermal pad |
| Kiểu lắp đặt | Surface Mount |
| Cấp MSL | 2 (1 year floor life) |
| Trạng thái RoHS | Compliant |
| Factory Programming Code | D04594 (custom frequency plan via ClockBuilder Pro) |
| Packaging | Tape & Reel (TR) |
| Quantity per Reel | 1000 |
Cấu hình chân SI5345A-D04594-GMR
| Chân 1 | IN0 — Reference clock input 0 (differential positive) |
| Chân 2 | IN0b — Reference clock input 0 (differential negative) |
| Chân 3 | VDD — Core supply 1.71 V to 1.89 V |
| Chân 4 | VDDA — Analog supply |
| Chân 5 | IN1 — Reference clock input 1 (differential positive) |
| Chân 6 | IN1b — Reference clock input 1 (differential negative) |
| Chân 7 | GND — Ground |
| Chân 8 | OUT0 — Clock output 0 (format programmable) |
| Chân 9 | OUT0b — Clock output 0 complementary |
| Chân 10 | VDDO — Output supply for bank 0 |
| Chân 11 | OUT1 — Clock output 1 |
| Chân 12 | OUT1b — Clock output 1 complementary |
| Chân 13 | GND — Ground |
| Chân 14 | OUT2 — Clock output 2 |
| Chân 15 | OUT2b — Clock output 2 complementary |
| Chân 16 | VDDO — Output supply for bank 1 |
| Chân 17 | OUT3 — Clock output 3 |
| Chân 18 | OUT3b — Clock output 3 complementary |
| Chân 19 | GND — Ground |
| Chân 20 | OUT4 — Clock output 4 |
| Chân 21 | OUT4b — Clock output 4 complementary |
| Chân 22 | VDDO — Output supply for bank 2 |
| Chân 23 | OUT5 — Clock output 5 |
| Chân 24 | OUT5b — Clock output 5 complementary |
| Chân 25 | GND — Ground |
| Chân 26 | OUT6 — Clock output 6 |
| Chân 27 | OUT6b — Clock output 6 complementary |
| Chân 28 | VDDO — Output supply for bank 3 |
| Chân 29 | OUT7 — Clock output 7 |
| Chân 30 | OUT7b — Clock output 7 complementary |
| Chân 31 | GND — Ground |
| Chân 32 | OUT8 — Clock output 8 |
| Chân 33 | OUT8b — Clock output 8 complementary |
| Chân 34 | VDDO — Output supply for bank 4 |
| Chân 35 | OUT9 — Clock output 9 |
| Chân 36 | OUT9b — Clock output 9 complementary |
| Chân 37 | GND — Ground |
| Chân 38 | SDA — I2C serial data |
| Chân 39 | SCL — I2C serial clock |
| Chân 40 | VDD — Core supply |
| Chân 41 | A0 — I2C address LSB |
| Chân 42 | GND — Ground |
| Chân 43 | nIRQ — Interrupt output (active low) |
| Chân 44 | nRST — Reset (active low) |
| Chân 45 | VDD — Core supply |
| Chân 46 | XO — Crystal oscillator driver output |
| Chân 47 | XI — Crystal oscillator input |
| Chân 48 | GND — Ground |
| Chân 49 | TEST — Test mode (tie to GND in normal operation) |
| Chân 50 | VDDA — Analog supply |
| Chân 51 | NC — Not connected |
| Chân 52 | NC — Not connected |
| Chân 53 | NC — Not connected |
| Chân 54 | NC — Not connected |
| Chân 55 | GND — Ground |
| Chân 56 | NC — Not connected |
| Chân 57 | NC — Not connected |
| Chân 58 | NC — Not connected |
| Chân 59 | VDD — Core supply |
| Chân 60 | NC — Not connected |
| Chân 61 | NC — Not connected |
| Chân 62 | NC — Not connected |
| Chân 63 | GND — Ground |
| Chân 64 | VDD — Core supply |
Ứng dụng tiêu biểu
SI5345A-D04594-GMR phù hợp cho 6 Áp dụngs: 100G/400G Ethernet Switch Timing, OTN/SONET/SDH Line Card Clocking, FPGA/ASIC Transceiver Reference Clock Tree, Wireless Base Station Timing, Broadcast Video Router Reference, Test & Measurement Instrumentation.
100G/400G Ethernet Switch Timing
The Si5345A-D04594-GMR's ten independently programmable outputs and sub-200 fs RMS jitter make it ideal as a single-chip reference tree for 100G/400G Ethernet switch ASICs. Each PHY typically needs a 156.25 MHz or 161.13 MHz reference, often in mixed LVDS and HCSL formats; the Si5345A can deliver up to ten of those references from one factory-programmed ClockBuilder Pro plan, eliminating multiple discrete oscillators. The QFN-64-EP package exposes a thermal pad that anchors the device to a ground pour for low-jitter ground-bounce performance.
Được đề xuất
OTN/SONET/SDH Line Card Clocking
OTN and SONET/SDH line cards require Stratum-3/3E-grade jitter performance on multiple reference outputs at 155.52 MHz, 311.04 MHz, and related multiples. The Si5345A-D04594-GMR delivers these frequencies with sub-200 fs RMS jitter while offering per-output format selection between LVDS and LVPECL to feed both legacy SONET framer ASICs and newer OTN mappers. Its I2C interface lets the host SoC change output enables and frequencies in-system during line-card bring-up.
Được đề xuất
FPGA/ASIC Transceiver Reference Clock Tree
Modern FPGAs and ASICs with multi-gigabit transceivers need multiple low-jitter reference clocks at 100 MHz, 122.88 MHz, 156.25 MHz, and other rates. The Si5345A-D04594-GMR's ten-output architecture allows one device to feed an entire transceiver bank, and the per-pin LVDS/LVPECL/HCSL output selection matches the input requirements of Xilinx, Intel (Altera), and Microchip FPGA transceivers. The factory -D04594 plan removes in-system NVM programming overhead during prototyping.
Được đề xuất
Wireless Base Station Timing
4G/5G base-station RRUs and BBUs require multiple sample-rate clocks (e.g., 122.88 MHz, 153.6 MHz, 245.76 MHz) with extremely low jitter to support high-order QAM modulation. The Si5345A-D04594-GMR's sub-200 fs RMS jitter and any-frequency flexibility let one IC serve the entire timing tree of a small-cell or macro base-station card. Its -40 C to +85 C industrial temperature range covers outdoor radio unit deployments.
Được đề xuất
Broadcast Video Router Reference
Broadcast video routers (SMPTE 424M, 425M, 2082) require ultra-low-jitter 148.35 MHz and 148.5 MHz references for SDI serializers and deserializers. The Si5345A-D04594-GMR provides these frequencies with any-format output selection, allowing direct drive of SDI cable drivers without external level translation. The factory -D04594 frequency plan guarantees deterministic frequencies at first power-up, which is critical for broadcast hardware that must boot into a known state.
Được đề xuất
Test & Measurement Instrumentation
High-end oscilloscopes, BERTs, and signal analyzers demand multiple clean reference clocks across the chassis. The Si5345A-D04594-GMR's factory programming removes the risk of in-system configuration failure and provides a deterministic, repeatable clocking scheme for production test instruments. Its low RMS jitter improves instrument phase-noise floor, which directly translates to better measurement accuracy at high modulation frequencies.
Được đề xuất
Tóm tắt các sản phẩm được đề xuất
Dữ liệu tham khảo kỹ thuật cho SI5345A-D04594-GMR — so sánh, hướng dẫn thiết kế và thông tin tuân thủ.
Hướng dẫn chọn lựa
So sánh với các sản phẩm thay thế
| Tham số | Sản phẩm này | SI5345A-D04594-GM | SI5345A-D-GMR | SI5345A-D-GM | SI5344B-D-GM | SI5340A-D-GM |
|---|---|---|---|---|---|---|
| Package | QFN-64-EP (9x9 mm) | QFN-64-EP (9x9 mm) - same | QFN-64-EP (9x9 mm) - same | QFN-64-EP (9x9 mm) - same | QFN-44 - DIFFERENT (smaller) | QFN-44 - DIFFERENT (smaller) |
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Number of Outputs | 10 | 10 | 10 | 10 | 4 (-60%) | 4 (-60%) |
| Max Output Frequency | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz | 1028 MHz |
| Factory Programming | Yes (-D04594) | Yes (-D04594) | No (unprogrammed) | No (unprogrammed) | No | No |
| RMS Jitter | < 200 fs | < 200 fs | < 200 fs | < 200 fs | < 200 fs | < 300 fs |
| Control Interface | I2C | I2C | I2C | I2C | I2C | I2C/SPI |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| RoHS Status | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Bảo phân biệt quan trọng
- Factory-programmed frequency plan eliminates in-system NVM programming risk (vsSI5345A-D-GMR)
- 10 outputs vs 4 in lower-count variants (vsSI5344B-D-GM)
- Per-pin format selection (LVDS/LVPECL/HCSL/CML/CMOS/HSTL/SSTL) (vsSI5340A-D-GM)
Ghi chú thiết kế
Per the Skyworks Si5345 datasheet, place a 0.1 uF X7R ceramic capacitor as close as possible (within 2 mm) to each VDD, VDDA, and VDDO pin, paired with a 10 uF bulk capacitor on each supply rail. The exposed thermal pad must be soldered to a continuous ground pour stitched with at least 25 thermal vias (0.3 mm drill, 0.6 mm pitch) to provide both electrical reference and a low-impedance thermal path. Keep clock output traces 50 ohm differential (100 ohm differential) with length matching within 5 mils across each pair.
Route the crystal traces (XI, XO) as short and symmetric as possible, surrounded by a ground guard trace on both sides to keep stray capacitance below 5 pF. Use a fundamental-mode crystal with ESR < 50 ohms and load capacitance specified by ClockBuilder Pro for the -D04594 plan. If the application is noise-sensitive, isolate the analog VDD/VDDA pins from the digital VDD with a ferrite bead to prevent digital switching noise from coupling into the PLL loop.
The -D04594 factory programming is loaded at production; do NOT issue an in-system NVM reprogramming command unless intentionally overriding the factory image, because the resulting clock tree may not match the order code on the reel label. The I2C address is set by the A0 pin (typically 0x6E or 0x6F); verify against the ClockBuilder Pro header file before polling. Outputs that are disabled at the Si5345A still draw leakage current - tie unused complementary outputs (OUTxb) to GND through 50 ohm if not used.
Thông tin tuân thủ
RoHS compliant per JLCPCB, Mouser, and DigiKey listings. Not AEC-Q100 qualified - this part targets industrial/commercial, not automotive. Halogen-free and lead-free per Skyworks product family standards.
