ADC12DL040CIVSX vs ADC12DL040CIVS 比較
詳細並排比較 ADC12DL040CIVSX 由 Texas Instruments 與 ADC12DL040CIVS 由 Texas Instruments. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Texas Instruments
ADC12DL040CIVSX - Dual 12-Bit 40 MSPS ADC | Texas Instruments
ADC12DL040CIVSX ✓ 啟用中Texas Instruments
ADC12DL040CIVS - Dual 12-Bit 40 MSPS 3V ADC | Texas Instruments
ADC12DL040CIVS Nrnd規格比較
| 參數 | ADC12DL040CIVSX | ADC12DL040CIVS |
|---|---|---|
| 品牌 | Texas Instruments | Texas Instruments |
| 類別 | ADC/DAC | ADC/DAC |
| 生命週期狀態 | 啟用中 | NRND |
| 解析度 | 12 bit | 12 Bits |
| Number of Channels | 2 (Dual) | 2 (dual, simultaneous sampling) |
| Sampling Rate (per channel) | 40 MSPS | — |
| Architecture | Pipelined CMOS | Pipelined CMOS |
| 輸入電壓範圍 | 0.0 V to 2.6 V (analog input) | — |
| Analog Supply Voltage | 3 V (single supply) | 3.0 V (2.7 V to 3.6 V range) |
| Power Dissipation | 210 mW (typical, 3V, 40 MSPS) | — |
| Power Consumption per Channel | 105 mW (typical) | — |
| Data Interface | Parallel CMOS | — |
| Digital Output Format | [DATA_NEEDED: digital output format/code] | — |
| Reference Type | Internal (on-chip reference) | — |
| 工作溫度範圍 | -40C to +85C (Industrial) | — |
| 封裝 / 外殼 | 64-TQFP (PAG) 10x10 mm | — |
| 安裝類型 | Surface Mount | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Sample-and-Hold | Yes (integrated, per channel) | Internal, dual |
| Differential Nonlinearity (DNL) | [DATA_NEEDED: DNL bits LSB] | — |
| Integral Nonlinearity (INL) | [DATA_NEEDED: INL bits LSB] | — |
| Signal-to-Noise Ratio (SNR) | [DATA_NEEDED: SNR dB at 40 MSPS] | — |
| RoHS 狀態 | Compliant | — |
| Lead-Free | Yes | — |
| Sample Rate (per channel) | — | 40 MSPS |
| Digital Output Driver Supply | — | 2.4 V to 3.6 V (separate DVDD) |
| Power Dissipation (typical) | — | 210 mW |
| Power-Down Mode | — | Yes |
| SNR (fIN = 10 MHz) | — | 69 dB (typical) |
| SFDR (fIN = 10 MHz) | — | 85 dB (typical) |
| DNL (Differential Non-Linearity) | — | ±0.3 LSB (typical) |
| INL (Integral Non-Linearity) | — | [DATA_NEEDED: INL spec] |
| Internal Reference | — | Yes (factory-trimmed, not user-adjustable) |
| Duty Cycle Stabilizer | — | Yes |
| Multiplexed Output Mode | — | Yes (channels share single 12-bit bus) |
| Output Format | — | Straight Binary, offset binary, 2's complement (per pin strapping) |
| Input Clock | — | Single-ended or differential; 50 Ω terminated internally |
| 工作溫度 | — | -40 °C to +85 °C (industrial) |
| 封裝 | — | 64-pin TQFP (PAG) 10x10 mm, surface-mount |
| MSL (Moisture Sensitivity Level) | — | [DATA_NEEDED: MSL level] |
| Lead Finish / RoHS | — | Lead-free / RoHS status depends on orderable suffix (see datasheet ordering info) |