CDK8307AILP64 vs CDK8307BILP64 比較

詳細並排比較 CDK8307AILP64 由 MaxLinear 與 CDK8307BILP64 由 MaxLinear. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

MaxLinear
CDK8307BILP64 CDK8307BILP64 - Octal 12/13-bit 40MSPS LVDS ADC | MaxLinear

CDK8307BILP64 - Octal 12/13-bit 40MSPS LVDS ADC | MaxLinear

CDK8307BILP64 ✓ 啟用中

規格比較

參數 CDK8307AILP64 CDK8307BILP64
品牌 MaxLinear MaxLinear
類別 ADC/DAC ADC/DAC
生命週期狀態 啟用中 啟用中
解析度 12/13-bit (selectable) 12-bit or 13-bit (programmable)
Number of Channels 8 (simultaneous sampling) 8
Sample Rate Range 20 / 40 / 50 / 65 / 80 MSPS —
Architecture Pipelined ADC with proprietary core —
Output Interface Serial LVDS —
Reference Internal reference (integrated) Internal (integrated bandgap reference)
供應電壓 [DATA_NEEDED: supply voltage] [DATA_NEEDED: supply voltage rating]
Power Dissipation (Typ) Ultra-low power (per-channel shutdown) —
Shutdown Modes Per-channel + full-chip idle (via external pin) —
Control Interface Serial programming interface (SPI-style) Serial control interface
FPGA Compatibility Designed to interface with major FPGA vendors —
封裝 64-pin QFN (ILP64) 64-pin QFN (LP suffix)
安裝類型 Surface Mount Surface Mount
工作溫度範圍 [DATA_NEEDED: temperature range] [DATA_NEEDED: operating temperature range]
RoHS 狀態 Compliant Compliant
Original Brand Cadeka / Exar (now MaxLinear) —
Product Type — Octal Analog-to-Digital Converter (ADC)
Sample Rate (per channel) — 20 / 40 / 50 / 65 MSPS
Total Power Dissipation — 280 mW
Data Output Interface — Serial LVDS
Input Type — Differential analog inputs (one per channel)
Clock Architecture — External reference clock with integrated PLL (x12 or x14 multiplication)

資料表與資源

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