EP1810GI-45 vs EP1810JC35 比較
詳細並排比較 EP1810GI-45 由 Altera 與 EP1810JC35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810GI-45 | EP1810JC35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 48 |
| Flip-Flops | 48 | — |
| Propagation Delay (tpd) | 45 ns | — |
| Speed Grade | -45 | — |
| Technology | CMOS | — |
| Package Type | Ceramic Pin Grid Array with UV window | — |
| 腳位數 | 68 | — |
| 安裝類型 | Through-Hole | — |
| Programmable | Yes (UV-erasable, electrically programmable) | — |
| RoHS 狀態 | Non-compliant (ceramic PGA) | [DATA_NEEDED: RoHS compliance for EP1810JC35] |
| Lead-Free | No | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (Commercial) |
| 供應電壓 | [DATA_NEEDED: VCC range] | — |
| Product Type | — | UV-erasable / OTP Complex PLD (EPLD) |
| Logic Gates (typ.) | — | [DATA_NEEDED: logic gates count] |
| Maximum User I/O Pins | — | [DATA_NEEDED: user I/O count for PLCC-68] |
| Propagation Delay (tPD) | — | 35 ns |
| 最大時脈頻率 | — | 40 MHz |
| Supply Voltage (VCC max) | — | 5.25 V |
| Supply Voltage (VCC min) | — | [DATA_NEEDED: VCC minimum] |
| Process Technology | — | CMOS EPROM cell |
| 封裝 | — | PLCC-68 (J-lead, ceramic) |
| Package Code | — | QCCJ |
| Terminal Form | — | J-BEND |
| Number of Terminals | — | 68 |
| Programming | — | UV-erase (windowed) or OTP |
| Development Tool | — | Altera MAX+plus II / A+plus |