EP1810JC-35 vs EP1810JI-35 比較
詳細並排比較 EP1810JC-35 由 Intel 與 EP1810JI-35 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810JC-35 | EP1810JI-35 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Classic EPLD (EP1810) | Classic EPLD |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | — |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | — |
| 最大時脈頻率 | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | CMOS EPROM (UV-erasable) |
| Supply Voltage (Vcc) | 5 V (nominal) | — |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | — |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| 工作溫度範圍 | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| RoHS 狀態 | Compliant (per Altera listing) | [DATA_NEEDED: RoHS compliance for ceramic windowed JLCC] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| 安裝類型 | Surface Mount (J-Lead) | Through-Hole (J-lead) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Macrocells | — | 48 |
| Logic Array Blocks | — | 8 LABs of 16 macrocells |
| Dedicated Inputs | — | 48 |
| Pin-to-Pin Propagation Delay (tPD) | — | 35 ns |
| Speed Grade | — | -35 |
| 封裝 | — | 28-pin JLCC (J-leaded ceramic, windowed) |
| 工作溫度 | — | -40C to +85C (Industrial) |
| 供應電壓 | — | 5 V (typical classic EPLD) |
| Programmability | — | UV-erase, windowed for lab reprogram |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Programming Interface | — | JEDEC fuse file via legacy programmer |