EP1810LC-35 vs EP1810LC-25 比較
詳細並排比較 EP1810LC-35 由 Rochester Electronics 與 EP1810LC-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ 最後購買機會
規格比較
| 參數 | EP1810LC-35 | EP1810LC-25 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | Classic EP1810 | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V (TTL-compatible) |
| Technology | CMOS, UV-erasable EPROM | CMOS EPLD (erasable programmable logic device) |
| 封裝 | 68-pin PLCC (J-Lead) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| 安裝類型 | Surface Mount (socketable) | Surface Mount |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade for LC package] |
| I/O Pins | [DATA_NEEDED: I/O count exact] | 48 |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | Global + Local buses |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| RoHS 狀態 | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Lead-Free | [DATA_NEEDED] | — |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| Propagation Delay (tPD) | — | 25 ns |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Package Code | — | LC = 68-pin JLCC |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| 生命週期狀態 | — | Obsolete (legacy Altera Classic family) |