EP1810LC-35T vs EP1810LC-30 比較
詳細並排比較 EP1810LC-35T 由 Intel 與 EP1810LC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1810LC-35T | EP1810LC-30 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | EP1810 Classic EPLD | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 900 | — |
| Macro Cells | 48 | — |
| Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS | CMOS, low-power (LC) |
| Logic Compatibility | 100% TTL emulation | — |
| 封裝 | 68-pin PLCC (Plastic Leaded Chip Carrier) | JLCC-68 (68-pin J-Lead ceramic chip carrier) |
| Package Suffix | T = Tape and Reel | — |
| 工作溫度 | 0 C to +70 C (Commercial) | [DATA_NEEDED: temperature grade] |
| 安裝類型 | Surface Mount (PLCC socket or direct solder) | — |
| Programming Method | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II | — |
| RoHS 狀態 | Non-compliant (legacy PLCC product) | unknown (legacy ceramic package) |
| Logic Family Replacement Target | 74LS low-power Schottky TTL | — |
| Family | — | Altera Classic EPLD |
| Macrocells | — | 48 |
| Flip-Flops | — | 48 (one per macrocell) |
| Speed Grade (tPD) | — | 30 ns |
| 供應電壓 | — | 5 V (typical) |
| Programming | — | Device programmer or JTAG |
| Standby Current | — | [DATA_NEEDED: ICC standby] |
| 腳位數 | — | 68 |
| Number of I/O Pins | — | [DATA_NEEDED: I/O count] |
| Logic Blocks | — | 48 macrocells |