EP1830-20CFN vs EP1810LC-25 比較
詳細並排比較 EP1830-20CFN 由 Texas Instruments 與 EP1810LC-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1830-20CFN | EP1810LC-25 |
|---|---|---|
| 品牌 | Texas Instruments | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Technology | CMOS EPROM | CMOS EPLD (erasable programmable logic device) |
| Macrocell Count | 48 | — |
| Propagation Delay (tPD) | 22 ns | 25 ns |
| Maximum Supply Voltage | 5.25 V | — |
| I/O Pins | 48 | 48 |
| Dedicated Inputs | 12 | 12 |
| 封裝 | PLCC-68 (QCCJ, J-lead) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Terminal Pitch | 1.27 mm | — |
| Terminal Form | J-Bend | — |
| Package Code | QCCJ | LC = 68-pin JLCC |
| Package Shape | Square | — |
| Operating Temperature Grade | Commercial (0C to 70C) | — |
| Typical Operating Current | 20 mA at 1 MHz | — |
| Maximum Counter Frequency | 50 MHz (4 x 12-bit counters) | — |
| Speed Grade | -20 | — |
| Configuration Memory | Non-volatile EPROM (UV-erasable) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| Macrocells | — | 48 |
| External Clock Inputs | — | 4 |
| Supply Voltage (VCC) | — | 5 V (TTL-compatible) |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| 安裝類型 | — | Surface Mount |
| Programmable Interconnect | — | Global + Local buses |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| 生命週期狀態 | — | Obsolete (legacy Altera Classic family) |
| 工作溫度 | — | [DATA_NEEDED: temperature grade for LC package] |