EP1S40F1020C5N vs EP1S40F1020C5GA 比較

詳細並排比較 EP1S40F1020C5N 由 Intel 與 EP1S40F1020C5GA 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1S40F1020C5N EP1S40F1020C5GA
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family Stratix —
Logic Elements (LE) 41,250 41,250
Logic Array Blocks (LAB) 4,125 —
Embedded Memory Bits 3,423,744 —
Maximum User I/Os 773 —
Process Technology 130 nm CMOS —
Core Voltage 1.5 V —
Maximum Internal Frequency 500 MHz —
Speed Grade C5 (commercial, slowest) C5
Temperature Grade Commercial Extended —
封裝 1020-ball FBGA (FineLine BGA) 1020-BBGA (FineLine BGA)
安裝類型 Surface Mount Surface Mount
PLLs Yes (multiple, enhanced PLL) —
DSP Blocks Yes (embedded multiplier blocks) Embedded multiplier blocks (count per Stratix datasheet family)
External Memory Support DDR SDRAM, QDR SRAM, FCRAM, ZBT —
Configuration Scheme Passive serial, active serial, JTAG —
RoHS 狀態 Unknown - verify with manufacturer Unknown - non-GA suffix commercial part
Lead-Free Unknown Yes (per Altera/Intel policy at release)
Series — Stratix
Total RAM Bits — 3,423,744
User I/O Count — 773
工作溫度 — 0C to +85C (Commercial)
Process Node — 0.13 µm CMOS with 9-layer metal
Supply Voltage (Core) — [DATA_NEEDED: VCCINT value]
I/O Bank Count — [DATA_NEEDED: bank count]
PLL Count — Up to 12 enhanced PLLs (per Stratix family)
High-Speed Transceivers — Up to 12 channels (per Stratix family, variant dependent)
Configuration Method — JTAG, Passive Serial, Altera EPC device
MSL 等級 — [DATA_NEEDED: MSL rating]

資料表與資源

瀏覽所有產品 建立 BOM 索取報價