EP1S60F1020C7 vs EP1S60F1020C6N 比較

詳細並排比較 EP1S60F1020C7 由 Altera 與 EP1S60F1020C6N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP1S60F1020C7 EP1S60F1020C6N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Series Stratix Stratix
Family Stratix (EP1S60) Stratix (EP1S)
Logic Elements 57,120 —
Total Memory Bits 5,215,104 —
Maximum User I/O 773 —
封裝 1020-BBGA, FCBGA, 33 x 33 mm, 1.0 mm pitch —
安裝類型 Surface Mount Surface Mount (BGA)
Logic Family CMOS —
工作溫度 0C to +85C (Commercial) 0°C to +85°C (Commercial)
Core Supply Voltage 1.5 V —
Speed Grade 7 C6 (mid-tier)
Logic Cells / Logic Blocks 6,570 (per datasheet Section I nomenclature) —
DSP Blocks Embedded dedicated multiplier / adder blocks —
PLLs Up to 12 enhanced PLLs per die —
Configuration Method Serial or parallel with optional decompression —
MSL 等級 3 (per BGA moisture-sensitivity norms) [DATA_NEEDED: MSL rating]
RoHS 狀態 Compliant (lead-free) Compliant (per 'N' suffix)
Logic Elements (LEs) — 57,120
Logic Cells — 6,570 blocks (per chipdig datasheet summary)
Embedded RAM (Total Bits) — 5,215,104 bits
Embedded Multipliers — 773 (18x18)
Maximum User I/O Pins — Per datasheet, package-dependent (F1020 variant)
Package Type — 1020-ball FBGA (FineLine BGA), 33 x 33 mm, 1 mm pitch
Logic Family / Process — CMOS, 0.13 µm
供應電壓 — Per datasheet (Stratix Device Handbook Vol. 1)
Lead-Free / Pb-Free — Yes (suffix 'N')
Configuration — JTAG / Passive Serial / Fast Passive Parallel via MSEL pins
PLL Count — 12 (per Stratix family datasheet)
Memory Block Types — TriMatrix (M512, M4K, M-RAM)

資料表與資源

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