EP1SGX40FF1020C5 vs EP1SGX40DF1020C5ES 比較

詳細並排比較 EP1SGX40FF1020C5 由 Intel 與 EP1SGX40DF1020C5ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。

Intel

EP1SGX40FF1020C5 - Stratix GX FPGA, 41,250 LEs, 1020-BGA | Intel

EP1SGX40FF1020C5 Nrnd

Intel

EP1SGX40DF1020C5ES ✓ 啟用中

參數	EP1SGX40FF1020C5	EP1SGX40DF1020C5ES
品牌	Intel	Intel
類別	FPGA & CPLD	FPGA & CPLD
生命週期狀態	NRND	啟用中
Family	Stratix GX	—
Logic Elements	41,250	—
Configurable Logic Blocks (CLBs)	4,125	—
Total RAM Bits	3,423,744 bits	—
Number of I/O Banks	[DATA_NEEDED: number of I/O banks]	—
Transceiver Channels	20 (up to 3.125 Gbps)	—
Core Voltage	1.5 V (1.425 V to 1.575 V)	—
工作溫度	0C to +85C (commercial, -C5 speed grade)	0 C to 85 C
封裝	1020-ball FCBGA (FF), 1.00 mm pitch, 33 x 33 mm	—
Seated Height	3.50 mm	—
Process Technology	CMOS, 0.13 um	130 nm
Maximum User I/O	[DATA_NEEDED: max user I/O count]	—
DSP Blocks	[DATA_NEEDED: DSP block count]	—
PLLs	[DATA_NEEDED: PLL count]	—
安裝類型	Surface Mount	—
MSL 等級	[DATA_NEEDED: MSL rating]	—
RoHS 狀態	[DATA_NEEDED: RoHS status]	unknown
Product Type	—	Field-Programmable Gate Array (FPGA)
Logic Family	—	Stratix GX
Logic Technology	—	CMOS
Logic Cells	—	41,250 cells
Logic Array Blocks	—	4,125 LABs
Configurable I/O Connections	—	624 input and 624 output connections
供應電壓	—	1.5 V
Reported Maximum Frequency	—	5,000 MHz
Reported Maximum CLB Combinatorial Delay	—	7.49 ns
Alternative Listed Maximum Clock Frequency	—	6 MHz
Terminal Count	—	1,020 pins
Package Type	—	FC-FBGA-1020
Package Dimensions	—	33 mm x 33 mm
Ball Pitch	—	1 mm
Mounting Configuration	—	Surface-mount ball grid array
Terminal Form	—	Ball
Package Code	—	BGA
Configuration Method	—	[DATA_NEEDED: configuration method]
REACH Status	—	unknown
AEC-Q100 Qualification	—	unknown