EP1SGX40FF1020I6 vs EP1SGX40FF1020C7 比較
詳細並排比較 EP1SGX40FF1020I6 由 Altera 與 EP1SGX40FF1020C7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP1SGX40FF1020I6 | EP1SGX40FF1020C7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Series | Stratix® GX | Stratix GX |
| Family | EP1SGX40 | Stratix GX (EP1SGX40) |
| Logic Elements | 41,250 | — |
| Embedded Memory | 3,423,744 bits | — |
| User I/Os | 624 | — |
| Logic Array Blocks (LABs) | 41,250 | — |
| 封裝 | 1020-ball FineLine BGA | 1020-ball FC-FBGA (S-PBGA-B1020) |
| 安裝類型 | Surface Mount | Surface Mount |
| Core Voltage (VCCINT) | 1.5 V ±0.15 V | — |
| 工作溫度 | -40 °C to +100 °C (Industrial) | 0 °C to 85 °C (commercial) |
| Temperature Grade | I (Industrial) | — |
| Transceiver Channels | Up to 20 channels | 20 full-duplex 3.1875 Gbps + 14 dedicated full-duplex 1.25 Gbps |
| Max Transceiver Data Rate | 3.1875 Gbps | — |
| Transceiver Technology | CDR with embedded SERDES | — |
| Process Technology | CMOS | CMOS |
| Configuration | SRAM-based LUT | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Logic Elements (LE) | — | 41,250 |
| Configurable Logic Blocks (CLB) | — | 4,125 |
| Embedded Memory (bits) | — | 3,423,744 |
| User I/O Pins | — | 624 |
| Number of Logic Array Blocks (LAB) | — | 4,125 |
| Number of I/O Banks | — | 12 |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Speed Grade | — | 7 (-7, mid-speed) |
| Package Dimensions | — | 33 mm × 33 mm |
| Ball Pitch | — | 1.00 mm |
| Configuration Modes | — | PS, PPS, PPA, JTAG, AS |
| DSP Blocks (9-bit) | — | 176 |
| PLLs | — | 8 enhanced + per-transceiver PLLs |