EP20K100QC240-1XV vs EP20K100QC240-3N 比較

詳細並排比較 EP20K100QC240-1XV 由 Intel 與 EP20K100QC240-3N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K100QC240-1XV EP20K100QC240-3N
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 啟用中
Series APEX 20K —
Device Family APEX 20K (MultiCore architecture) —
System Gates 100,000 gates —
Logic Elements (Cells) 4,160 —
Embedded Memory 53,248 bits —
User I/Os 189 —
Dedicated Inputs 4 —
PLLs 4 —
Core Supply Voltage (VCCINT) 2.5 V nominal (2.375 V to 2.625 V) —
I/O Supply Voltage (VCCIO) 3.3 V / 5 V tolerant —
Propagation Delay (tpd) 2.5 ns —
Maximum Internal Frequency 250 MHz —
Process Technology 0.22 um CMOS —
封裝 240-pin PQFP (32 x 32 mm, 0.5 mm pitch) 240-BFQFP
安裝類型 Surface Mount (gull-wing leads) Surface Mount
工作溫度 0C to +85C (commercial) / -40C to +85C (industrial variant) 0 C to 85 C
Configuration Interface JTAG / serial (EPC configuration device) —
RoHS 狀態 Non-compliant (legacy PQFP, non-LEAD-FREE process) unknown
生命週期狀態 Obsolete / last-time-buy per Altera PCN —
Device Type — FPGA
Family — APEX-20K
Gate Count — 100000 gates
Logic Cells — 4160 cells
User I/O — 189 I/O
Distributed Memory — 53248 bits
Macrocells — 416 macrocells
供應電壓 — 2.375 V to 2.625 V
Nominal Supply — 2.5 V
Maximum Frequency — 167 MHz
腳位數 — 240 pins
Fabrication Process — 0.15 um all-layer copper-metal process
Package Pitch — 1.27 mm
Package Dimensions — 45 mm x 45 mm
AEC-Q100 — not_qualified

資料表與資源

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