EP20K100QC240-3V vs EP20K100QC240-3 比較

詳細並排比較 EP20K100QC240-3V 由 Intel 與 EP20K100QC240-3 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP20K100QC240-3 EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 - 189 I/O APEX-20K FPGA | Altera

EP20K100QC240-3 ✓ 啟用中

規格比較

參數 EP20K100QC240-3V EP20K100QC240-3
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 啟用中
Series APEX-20KE —
Family APEX-20K —
Logic Logic Elements / Cells 4,160 —
Total System Gates 100,000 —
Total RAM Bits 53,248 53248 bits
Number of User I/O 189 189
Number of Logic Blocks 53248 (LABs) —
Core Voltage 2.375 V to 2.625 V —
工作溫度 0C to +85C (Commercial) —
Maximum Frequency 167 MHz —
Process Technology 0.22 µm CMOS —
安裝類型 Surface Mount Surface Mount
封裝 240-BFQFP (32 x 32 mm) —
Speed Grade -3 (fastest APEX 20KE grade) -3
Lead-Free / RoHS Yes (-3V suffix) —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Manufacturer — Altera
FPGA Family — APEX-20K
Number of Logic Elements — 4160 cells
Typical Gate Count — 263000 gates
Core Supply Voltage — 2.5 V
最大時脈頻率 — 167 MHz (family rating)
Technology Process — 0.22 um
Package Type — 240-BFQFP
腳位數 — 240
工作溫度範圍 — 0 °C to +85 °C (commercial)
Propagation Delay — [DATA_NEEDED: propagation delay timing table]
Supported I/O Standards — [DATA_NEEDED: supported I/O standards]
Configuration / JTAG Interface — [DATA_NEEDED: configuration and JTAG interface details]
RoHS Compliance — [DATA_NEEDED: RoHS compliance for non-N version]

資料表與資源

瀏覽所有產品 建立 BOM 索取報價