EP20K400FI672-2N vs EP20K400FI672-2X 比較
詳細並排比較 EP20K400FI672-2N 由 Altera 與 EP20K400FI672-2X 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP20K400FI672-2N | EP20K400FI672-2X |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | APEX 20K | APEX 20K |
| Typical Gates | 400,000 | 400,000 system gates |
| Logic Elements / Cells | 16,640 | — |
| Maximum User I/O | 488 | — |
| Embedded Memory Bits | 212,992 bits | — |
| Embedded Array Blocks (EABs) | [DATA_NEEDED: EAB count per family datasheet] | — |
| Process Technology | 0.22 µm CMOS | 0.18 um CMOS, 6-metal |
| Core Voltage | 2.5 V | 1.8 V |
| Maximum Frequency | 200 MHz | — |
| 封裝 | 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA) | 672-ball BGA (FI672) |
| Package Body Size | 27 x 27 mm | — |
| Terminal Pitch | 1.0 mm | — |
| Propagation Delay | 3.1 ns | — |
| Speed Grade | -2 | -2X |
| 工作溫度 | Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant] | -40C to +85C (industrial) |
| 濕度敏感等級 (MSL) | 3 | — |
| Peak Reflow Temperature | 220 °C | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | Compliant (lead-free) | [DATA_NEEDED: RoHS compliance] |
| Configuration Modes | PS, PPS, PPA, JTAG | — |
| Supported I/O Standards | LVTTL, LVCMOS, SSTL, HSTL | — |
| Logic Elements | — | 16,640 |
| Embedded Memory | — | 212,992 bits |
| User I/O Pins | — | 496 |
| Package Code | — | BGA |
| Terminal Form | — | Ball |
| No. of Terminals | — | 672 |
| Package Shape | — | Square |
| I/O Voltage Support | — | 1.8V / 2.5V / 3.3V / 5V (MultiVolt) |
| Configuration Method | — | SRAM (serial EPROM or JTAG) |
| JTAG Support | — | Yes (IEEE 1149.1) |