EP20K600EFC144-2XN vs EP20K600CF672C8N 比較

詳細並排比較 EP20K600EFC144-2XN 由 Altera 與 EP20K600CF672C8N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP20K600EFC144-2XN EP20K600CF672C8N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 啟用中
Family APEX 20KE APEX 20KC
Logic Elements 24,576 —
Typical Gates 600,000 —
Maximum System Gates 1,053,840 —
Embedded RAM Bits 311,040 bits (~38 KB) —
Number of ESBs (Embedded System Blocks) [DATA_NEEDED: ESB count] —
Number of Multiplier Blocks [DATA_NEEDED: multiplier count] —
Number of PLLs 4 —
Number of I/O Pins [DATA_NEEDED: usable I/O count] —
Core Voltage 1.8 V —
I/O Voltage Banks Multi-voltage (LVTTL/LVCMOS/PCI) —
Process Technology 0.18 um CMOS, 6-layer metal —
Speed Grade -2 (mid-tier) —
封裝 144-ball FineLine BGA BGA-652, 45 x 45 mm, 1.27 mm pitch
工作溫度 -40C to +85C (industrial, 'N' suffix) 0°C to 85°C
RoHS 狀態 [DATA_NEEDED: RoHS] unknown
Configuration Method SRAM, IEEE 1532 / passive serial / passive parallel [DATA_NEEDED: configuration memory and programming method]
Device Type — SPLD
Product Type — FPGA / programmable logic device
Nominal Gate Capacity — 600K gates
Logic Elements or Cells — 24,320
Macros — 2,432
User I/O Count — 508
Package Terminals — 652 pins
Package Description — 672-pin FC-FBGA
供應電壓 — 1.8 V
Listed Frequency — 301.21 MHz
Propagation Delay — 1.48 ns
Fabrication Process — 0.15 µm
Interconnect Metal — All-layer copper metal
I/O Configuration — 508 user I/O
安裝類型 — Surface mount
REACH Status — unknown
AEC-Q100 Qualification — unknown
Core Current — [DATA_NEEDED: core supply current]
I/O Bank Voltage — [DATA_NEEDED: supported I/O voltage range]
Junction Temperature — [DATA_NEEDED: maximum junction temperature]
熱阻 — [DATA_NEEDED: junction-to-ambient thermal resistance]

資料表與資源

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