EP2A25F672C9 vs EP2A25F672C9N 比較
詳細並排比較 EP2A25F672C9 由 Altera 與 EP2A25F672C9N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A25F672C9 | EP2A25F672C9N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements (LE) | Approximately 25,000 | — |
| Macro Cells | 2432 | — |
| User I/O | 492 | — |
| 封裝 | 672-ball FCBGA (FineLine BGA) | 672-ball FineLine BGA (F672), 27 × 27 mm, 1.00 mm pitch |
| Package Dimensions | 27 mm x 27 mm | — |
| Ball Pitch | 1.0 mm | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.15 µm all-layer copper, up to 8 metal layers |
| Logic Family | CMOS | CMOS |
| Propagation Delay | 1.69 ns | 2.23 ns |
| 工作溫度 | 0°C to 85°C (Commercial) | 0 °C to +85 °C (commercial, C9 grade) |
| 供應電壓 | [DATA_NEEDED: core VCC voltage] | — |
| I/O Standards | LVTTL, LVCMOS, PCI, LVDS, HSTL, SSTL (multi-voltage 1.5/1.8/2.5/3.3 V) | — |
| Configuration | Passive Serial, Passive Parallel Synchronous, JTAG | — |
| Embedded Memory | ESBs for dual-port RAM, ROM, FIFO | Enhanced System Blocks (ESBs) for dual-port RAM |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| RoHS 狀態 | [DATA_NEEDED] | Compliant (per distributor listings) |
| Logic Elements / Cells | — | 24320 |
| System Gates | — | Approx. 900000 |
| Maximum User I/O | — | 492 |
| Operating Frequency | — | 236 MHz |
| Core Supply Voltage (VCCINT) | — | 1.425 V to 1.575 V (nominal 1.5 V) |
| Seated Height (max) | — | 2.100 mm |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+, SSTL-2/3, LVDS, LVPECL, PCML, HyperTransport |
| LVDS Data Rate | — | Up to 1 Gbps (True-LVDS) |
| Configuration Interface | — | Serial / Parallel PROM, JTAG, passive parallel (enhanced) |
| Design Software | — | Quartus II (v5.1 or later) |