EP2A40F672C6N vs EP2A40F672C7ES 比較
詳細並排比較 EP2A40F672C6N 由 Intel 與 EP2A40F672C7ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A40F672C6N | EP2A40F672C7ES |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements | 40,000 | 38400 |
| Maximum System Gates | 1,125,000 | — |
| Embedded RAM Bits | 442,368 | — |
| Embedded System Blocks (ESBs) | 160 | — |
| Maximum User I/O Pins | [DATA_NEEDED: maximum user I/O count] | — |
| Core Voltage | 1.5 V | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V | — |
| 封裝 | 672-ball FineLine BGA | 672-pin FC-FBGA (FineLine BGA) |
| 工作溫度 | Commercial (0C to +85C) | 0 °C to +85 °C (commercial) |
| Speed Grade | C6 (per part number suffix) | 7 |
| Configuration Methods | Passive Serial, Passive Parallel, JTAG | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status] |
| Process Technology | SRAM-based, 0.18 um (per family datasheet) | 0.15 µm CMOS |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| Typical Gates | — | 1.5 M |
| Maximum Logic Elements | — | 40960 |
| Maximum Macro Cells | — | 2560 |
| Maximum User I/O | — | 492 |
| Maximum Operating Frequency | — | 562 MHz |
| Core Voltage (VCCINT) | — | 1.5 V |
| I/O Voltage (VCCIO) | — | 3.3 V |
| Package Dimensions | — | 27 × 27 mm |
| Ball Pitch | — | 1.0 mm |
| Status Code | — | ES (Engineering Sample) |