EP2A40F672C7 vs EP2A40F672C6N 比較

詳細並排比較 EP2A40F672C7 由 Intel 與 EP2A40F672C6N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2A40F672C7 EP2A40F672C6N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete Obsolete
Family APEX II APEX II
Logic Elements 38,400 40,000
System Gates 1,500,000 —
Macro Cells 2,560 —
Maximum User I/O 492 —
Process Technology 0.15 µm CMOS, all-layer copper, up to 8 metal layers SRAM-based, 0.18 um (per family datasheet)
Core Voltage 1.5 V 1.5 V
I/O Voltage Support 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
Pin-to-Pin Delay 1.55 ns (C7 speed grade) —
Maximum Internal Frequency 562 MHz —
High-Speed Interface 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport —
PLLs 4 —
封裝 672-ball FC-FBGA (FineLine BGA) 672-ball FineLine BGA
Package Dimensions 27 x 27 mm, 1.0 mm pitch —
安裝類型 Surface Mount Surface Mount
Operating Temperature Grade Commercial (per 'C' suffix in speed grade) —
RoHS 狀態 Compliant [DATA_NEEDED: RoHS compliance status]
Lead-Free Yes —
Maximum System Gates — 1,125,000
Embedded RAM Bits — 442,368
Embedded System Blocks (ESBs) — 160
Maximum User I/O Pins — [DATA_NEEDED: maximum user I/O count]
I/O Standards Supported — LVTTL, LVCMOS, PCI, GTL+, SSTL, HSTL, 1.8V/2.5V/3.3V/5V
工作溫度 — Commercial (0C to +85C)
Speed Grade — C6 (per part number suffix)
Configuration Methods — Passive Serial, Passive Parallel, JTAG
PLL Count — [DATA_NEEDED: PLL count]

資料表與資源

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