EP3SL50F484I4LN vs EP3SL50F484I4LG 比較
詳細並排比較 EP3SL50F484I4LN 由 Altera 與 EP3SL50F484I4LG 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP3SL50F484I4LG - Stratix III L FPGA, 47.5K LE, 484-FCBGA | Altera (Intel)
EP3SL50F484I4LG Nrnd規格比較
| 參數 | EP3SL50F484I4LN | EP3SL50F484I4LG |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Product Type | Field Programmable Gate Array (FPGA) | — |
| Device Family | Stratix III L | — |
| Logic Cells | 47,500 | — |
| Embedded Memory | 2,184,192 bits | 2,184,192 bits (273 KB) |
| User I/O | 296 | — |
| Logic Array Blocks | 1,900 LABs | — |
| Listed Frequency | 717 MHz | — |
| Process Technology | CMOS | — |
| 封裝 | 484-BBGA, FCBGA | 484-Ball FCBGA (FBGA) |
| Package Description | FBGA-484 | — |
| Terminal Count | 484 | — |
| Terminal Form | Ball | — |
| Package Body Material | Plastic/Epoxy | — |
| Lead-Free Status | Lead free | — |
| Operating Temperature Grade | Industrial | — |
| I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Transceiver Count | [DATA_NEEDED: transceiver count] | — |
| Core Voltage | [DATA_NEEDED: core voltage] | — |
| I/O Voltage | [DATA_NEEDED: I/O voltage] | — |
| Junction Temperature | [DATA_NEEDED: junction temperature] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Family | — | Stratix III L |
| Series | — | EP3SL50 |
| Logic Elements | — | 47,500 |
| User I/Os | — | 296 |
| 安裝類型 | — | Surface Mount |
| 工作溫度 | — | -40C to +100C (Industrial) |
| Speed Grade | — | I4 (fast) |
| 供應電壓 | — | 0.85 V / 1.1 V / 1.2 V / 2.5 V / 3.3 V (multi-rail) |
| Process Node | — | 40 nm |
| Lead-Free | — | Yes |
| Total I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Transceivers | — | [DATA_NEEDED: transceiver channel count] |
| Configuration Memory | — | SRAM-based |
| Configuration Interface | — | JTAG / Passive Serial / Fast Passive Parallel |