EP610IDC-15 vs EP610DM-35 比較
詳細並排比較 EP610IDC-15 由 Intel 與 EP610DM-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610IDC-15 | EP610DM-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | Obsolete |
| Device Family | Altera Classic EPLD | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 15 ns | 35 ns |
| Maximum Frequency | 66 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (single supply) |
| 工作溫度 | 0C to +70C (commercial) | — |
| Process Technology | CMOS, UV-erasable / OTP | — |
| 封裝 | 24-pin CerDIP (ceramic DIP) | 24-pin CDIP (CERDIP) with UV window |
| 安裝類型 | Through-hole | — |
| I/O Pins | 24 (per package; macrocell-programmable) | 24 dedicated I/O (input + bidirectional) |
| Logic-Block Architecture | AND/OR macrocell array with programmable flip-flops | — |
| Program/Erase | UV-erasable, OTP-compatible | — |
| Development Tool | MAX+PLUS II | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status of CerDIP variant] | Non-compliant (contains lead, hermetic CERDIP) |
| Programming Current | 11.0 mA typical (per Classic family datasheet) | — |
| Manufacturer | — | Altera (Rochester Electronics authorized stock) |
| Part Family | — | Classic EPLD |
| Logic Family | — | PAL-type EPLD, CMOS, UV-erasable |
| Number of Macrocells | — | 16 |
| Number of Gates | — | 300 |
| Pipelined Data Rate (fMAX) | — | 100 MHz |
| Temperature Grade (M) | — | Military -55°C to +125°C |
| Programmability | — | UV-erasable, reprogrammable |
| 工作溫度範圍 | — | -55°C to +125°C |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |