EP610IPC-10 vs EP610DC-15 比較
詳細並排比較 EP610IPC-10 由 Altera 與 EP610DC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610IPC-10 | EP610DC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Programmable Gates | 300 usable gates | — |
| Macrocells | 16 | 16 |
| Maximum Operating Frequency | 100 MHz | — |
| Propagation Delay (tPD) | 15 ns (commerical -10 grade) | 15 ns (speed grade -15) |
| Product Terms | 160 total | — |
| Dedicated Inputs | 4 | 20 |
| I/O Pins | 16 | — |
| Total Input Pins | 20 | — |
| 供應電壓 | 5 V | — |
| Architecture | Turbo-only AND-OR-NOT, PAL-type | UV-erasable CMOS PAL-type |
| Technology | CMOS EPROM (UV-erasable / OTP) | CMOS |
| 封裝 | 24-pin PDIP (Plastic DIP) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| 工作溫度 | -40C to +85C (industrial) | 0C to 70C (commercial) |
| Programming Method | Altera programming hardware (UV erase for I grade, OTP for C grade) | JEDEC fuse map, UV erasure |
| TTL Emulation | 100% TTL compatible | — |
| Product Family | — | Classic EPLD (EP610) |
| Logic Expanders | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Total Product Terms | — | 160 |
| Maximum Internal Clock Frequency | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| 安裝類型 | — | Through-Hole |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status] |