EP910DC-15 vs EP910ILC-15N 比較
詳細並排比較 EP910DC-15 由 Altera 與 EP910ILC-15N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete規格比較
| 參數 | EP910DC-15 | EP910ILC-15N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic |
| Device Density | 900 usable gates | — |
| Macrocells | 24 | — |
| Logic Elements | [DATA_NEEDED: exact LE count] | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Pins | 12 | — |
| Flip-Flops | 10 | — |
| Product Terms per Macrocells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | 15 ns |
| Speed Grade | 15 | — |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V (5 V nominal) |
| 工作溫度 | 0C to +70C (commercial) | 0 C to +70 C (commercial) |
| Technology | CMOS EPROM, UV-erasable | — |
| 封裝 | 24-pin ceramic DIP (DC) | PLCC-44 (J-lead, surface mount) |
| 安裝類型 | Through-Hole | Surface Mount |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: not explicitly stated in verified data] | Compliant |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 450 |
| Macro Cells | — | 24 |
| Maximum Operating Frequency | — | 66.6 MHz |
| User I/O Pins | — | 36 |
| Dedicated Input Pins | — | 16 |
| Process Technology | — | CMOS EPROM (one-time programmable) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming | — | EPROM / JTAG (Classic EP-series) |