EP910IDC-15 vs EP910ILC-12 比較
詳細並排比較 EP910IDC-15 由 Altera 與 EP910ILC-12 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910IDC-15 | EP910ILC-12 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Manufacturer | Altera (now Intel PSG) | — |
| Family | Classic EPLD | Altera EP910 Classic EPLD |
| Equivalent Gates | 450 | — |
| Macrocells | 24 | — |
| Flip-Flops | 48 | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Frequency (fCNT) | 66.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| 封裝 | 40-pin CDIP (Ceramic DIP, through-hole) | 28-PLCC (J-Lead, 11.5 x 11.5 mm) |
| Terminal Count | 40 | — |
| Terminal Form | Through-Hole | — |
| Temperature Grade | Commercial (0C to +70C) | — |
| Programmable Security Bit | Yes | — |
| On-board Test Circuitry | Yes | — |
| Logic Type | UV Erasable EPROM-based | — |
| I/O Pins | 24 | — |
| Dedicated Inputs | 10 | — |
| Programming Technology | EPROM (UV-erasable) | — |
| RoHS 狀態 | non_compliant (ceramic DIP contains lead) | [DATA_NEEDED: RoHS status] |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | — | 24 |
| Usable Gates | — | 450 (typical) |
| Propagation Delay (tPD) | — | 12 ns (max) |
| Nominal Supply | — | 5 V |
| Memory Technology | — | UV-erasable CMOS EPROM |
| 安裝類型 | — | Surface Mount |
| 工作溫度 | — | -40 °C to +85 °C (industrial grade, 'I' suffix) |
| Configuration Storage | — | Non-volatile EPROM (instant-on) |
| Programming Method | — | Altera programming algorithm (serial/parallel master-slave) |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |
| 腳位數 | — | 28 |
| Feedback Paths | — | 16 dedicated |