EP910ILC-15 vs EP910IPC-15 比較
詳細並排比較 EP910ILC-15 由 Intel 與 EP910IPC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910ILC-15 | EP910IPC-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD | — |
| Series | EP910 | — |
| Logic Gates | 450 | — |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 15 ns | 15 ns |
| Maximum Operating Frequency | 83.33 MHz | — |
| 供應電壓 | 5 V | — |
| 記憶體類型 | EPROM (UV-erasable) | — |
| 工作溫度 | -40C to +85C (industrial) | 0C to +70C (commercial, IPC suffix) |
| 封裝 | 44-pin PLCC (J-lead) | PDIP-40 (Plastic DIP, 40-pin) |
| 安裝類型 | Surface Mount (SMT) | Through-Hole |
| Propagation Class | -15 speed grade | — |
| Storage Condition | Dry cabinet, humidity-controlled | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: rohs status not confirmed in verified data] |
| Device Family | — | Altera Classic EPLD (EP910 series) |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Architecture | — | PAL-type, CMOS |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Process Technology | — | CMOS |
| Programming Method | — | JEDEC fuse map via Altera EPLD programmer |
| 腳位數 | — | 40 |