EP910ILC-25 vs EP910ILI-25 比較
詳細並排比較 EP910ILC-25 由 Intel 與 EP910ILI-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910ILC-25 | EP910ILI-25 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | EP910 Classic EPLD | — |
| Macrocells | 24 | 24 |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 25 ns | 25 ns |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | CMOS, EPROM |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| 封裝 | 44-pin JLCC (windowed ceramic) | PLCC-44 (windowed ceramic, J-lead) |
| 安裝類型 | Surface Mount | — |
| 工作溫度 | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| 供應電壓 | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| RoHS 狀態 | non_compliant (ceramic windowed package) | Non-compliant (windowed ceramic package) |
| 生命週期狀態 | Obsolete - last time buy was late 1990s | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Series | — | EP910 (Classic EPLD) |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Product Terms | — | 240 (maximum) |
| Architecture | — | PAL-type with global interconnect bus |
| Operating Voltage | — | 5 V (4.75 V to 5.25 V) |
| Programming Method | — | UV-erasable (windowed), MAX+PLUS II programmer |
| Logic Test Circuitry | — | On-board JTAG-compatible test |