EP910IPC-15 vs EP910PI-15T 比較
詳細並排比較 EP910IPC-15 由 Altera 與 EP910PI-15T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910IPC-15 | EP910PI-15T |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | Classic EPLD (Erasable Programmable Logic Device) |
| Architecture | PAL-type, CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | 15 ns max (speed grade -15) |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| 工作溫度 | 0C to +70C (commercial, IPC suffix) | [DATA_NEEDED: industrial/commercial temp range] |
| 封裝 | PDIP-40 (Plastic DIP, 40-pin) | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| 安裝類型 | Through-Hole | Through-Hole |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | — |
| 腳位數 | 40 | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Family | — | Altera Classic EPLD (EP910 series) |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| 供應電壓 | — | 4.5 V to 5.5 V (5 V nominal) |
| Technology | — | CMOS EEPROM (electrically erasable) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |
| Programming | — | JEDEC-standard, serial/parallel programmer |