EP910LC44-35 vs EP910LC-35T 比較
詳細並排比較 EP910LC44-35 由 Intel 與 EP910LC-35T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC44-35 | EP910LC-35T |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | Classic EPLD (OT sub-family) | Classic EPLD (EP910) |
| Architecture | PAL-type AND/OR array | — |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns (max) | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Total Inputs | 36 | — |
| I/O Pins | 24 | — |
| Global Clocks | 2 | — |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| 封裝 | 44-pin PLCC (J-leaded) | PLCC-44 (J-lead) |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket or solder) |
| Process Technology | CMOS | CMOS (EPROM-based) |
| Programmability | UV-erasable (windowed ceramic) | — |
| Logic Capacity | — | 450 usable gates |
| Maximum Operating Frequency | — | 28.6 MHz |
| User I/O Pins | — | 36 |
| Erasure Method | — | UV-erasable window (ceramic package) / OTP (plastic) |
| Programming | — | Altera programming hardware + MAX+PLUS II |
| MSL 等級 | — | MSL 3 (168 hours) |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS status not in verified data] |