EPC16C100T vs EPC16QC100II 比較

詳細並排比較 EPC16C100T 由 Intel 與 EPC16QC100II 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16C100T EPC16QC100II
品牌 Intel Altera
類別 FPGA & CPLD Memory ICs
生命週期狀態 NRND NRND
記憶體容量 16 Mb —
Device Type Enhanced Configuration Device —
Supported FPGAs Stratix, Cyclone, APEX, Mercury (LUT-based) —
Configuration Schemes PS, PPS, FPP, PPA, JTAG —
介面 Serial / Parallel / JTAG (IEEE 1149.1) —
Core Voltage 3.3 V —
I/O Voltage 1.8 V to 3.3 V —
Programmability In-system via JTAG In-System Programmable via IEEE 1149.1 (JTAG)
封裝 100-pin PQFP 100-pin PQFP (Plastic Quad Flat Pack)
Lead Pitch 0.65 mm —
安裝類型 Surface Mount —
Compression Support Yes (Stratix / Stratix II) Yes (reduces on-PROM footprint vs uncompressed bitstream)
Multi-Device Configuration Yes (daisy chain) —
Remote Update Yes —
工作溫度 -40C to +85C (industrial) -40C to +85C (Industrial)
記憶體類型 — FPGA Configuration PROM (Flash-based)
Memory Density — 16 Mbit
Supported FPGA Families — APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone
Configuration Mode — FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous)
Cascade Support — Yes (multi-PROM cascading supported)
Core Supply Voltage — 3.3 V
I/O Tolerance — 5 V tolerant configuration pins
Package Dimensions — 20 mm x 14 mm, 0.5 mm pitch
Lead Finish — Matte Tin (lead-free)
MSL 等級 — 3 (per JEDEC J-STD-020)
RoHS 狀態 — Compliant
Configuration Pins — DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE

資料表與資源

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