EPC16QC100T vs EPC16QC-100T 比較

詳細並排比較 EPC16QC100T 由 Altera 與 EPC16QC-100T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QC100T EPC16QC-100T
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 NRND Obsolete
記憶體類型 In-System Programmable Configuration PROM Flash Configuration PROM (in-system programmable)
記憶體容量 16 Mbit —
介面 Serial FPGA configuration + JTAG (IEEE 1149.1) —
Supply Voltage (VCC) 3.3 V —
Programmability In-System Programmable via JTAG —
Daisy-Chain Support Yes (multi-device cascade) —
Data Compression Built-in decompression engine (up to 35% expansion) —
FPGA Compatibility Altera Cyclone, Stratix, ACEX, APEX series —
封裝 PQFP-100 (20 x 14 mm) 100-pin PQFP (20 x 14 mm), 0.65 mm pitch
安裝類型 Surface Mount Surface Mount
工作溫度 0C to +70C (commercial) [DATA_NEEDED: Operating temperature range]
Lead-Free / RoHS Depends on date code; verify per lot —
MSL 等級 3 (per JEDEC J-STD-020) [DATA_NEEDED: Moisture sensitivity level]
Programming Cycles 100 typical (per Altera datasheet) —
Packaging Suffix 'T' indicates Tape and Reel —
Max DCLK Frequency [DATA_NEEDED: max DCLK frequency] —
Access Time [DATA_NEEDED: serial access time] —
Memory Density — 16 Mbit (2 Mbyte)
Supported FPGA Families — Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
Configuration Data Width — 8-bit or 16-bit (cascaded dual-device mode)
Configuration Modes — Serial (single device), Parallel (two cascaded devices)
Data Compression Support — Yes (35% to 55% bitstream reduction typical)
JTAG / Boundary Scan — IEEE 1149.1 compliant, in-system programmable
供應電壓 — 3.3 V
Cascade Interface — nCE / nOE handshake for multi-device chains
Programming Interface — JTAG (IEEE 1149.1) and serial
Endurance — [DATA_NEEDED: Program/erase cycle rating]
Data Retention — [DATA_NEEDED: Data retention specification]
RoHS 狀態 — unknown
Lead-Free — unknown

資料表與資源

瀏覽所有產品 建立 BOM 索取報價