EPC1PC8N vs EPC1PC8CC 比較
詳細並排比較 EPC1PC8N 由 Intel 與 EPC1PC8CC 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC1PC8N | EPC1PC8CC |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | Obsolete | Obsolete |
| 記憶體類型 | OTP (One-Time Programmable) Configuration PROM | EPROM (OTP, UV-erasable window optional) |
| 記憶體容量 | 1 Mbit | 1 Mbit (1,048,576 bits) |
| 組織 | Serial (DCLK + DATA) | — |
| 供應電壓 | 3.0 V to 3.6 V | — |
| Supply Voltage (Typical) | 3.3 V | — |
| 介面 | Altera PS Serial / JTAG (IEEE 1149.1) | — |
| Programmability | In-system via JTAG; OTP after programming | — |
| Standby Current | [DATA_NEEDED: standby current uA] | — |
| Active Current | [DATA_NEEDED: active current mA] | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range C] | — |
| 封裝 | 8-pin PDIP (PC8N suffix) | PDIP-8 (Plastic DIP, 8-pin, 0.1" pitch) |
| 安裝類型 | Through-Hole | Through-Hole (DIP socketable) |
| RoHS 狀態 | Compliant (PC8N suffix indicates lead-free) | — |
| Configuration Mode | Serial (PS mode) | — |
| JTAG Compliance | IEEE Std. 1149.1-1990 boundary-scan | — |
| 功能 | — | FPGA Configuration PROM |
| Configuration Interface | — | Altera Passive Serial (PS), 4-wire (nSTATUS, nCONFIG, DCLK, DATA0) |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (typical 3.3 V) |
| Maximum DCLK Frequency | — | 17.6 MHz (17.6 Mb/s effective bitstream rate) |
| 工作溫度範圍 | — | [DATA_NEEDED: full industrial range from datasheet] |
| Cascade Support | — | Not supported in DIP-8 package (nCASC pin not exposed) |
| Programming Interface | — | JTAG via Altera Quartus / Quartus Prime ByteBlaster |
| Error Detection | — | Built-in CRC during configuration transfer |
| MSL 等級 | — | 1 (unlimited floor life) |
| Lead-Free / RoHS | — | Not lead-free (legacy Altera/Intel PC8 suffix is Sn-Pb finish); RoHS non-compliant variant |
| Compatible FPGA Families | — | ACEX 1K, APEX 20K, APEX II, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, FLEX 8000, MAX 7000B/AE/S, MAX 9000, Mercury, Stratix, Stratix II, Arria |
| 腳位數 | — | 8 |