EPC2L20 vs EPC2LI20 比較

詳細並排比較 EPC2L20 由 Altera 與 EPC2LI20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2L20 EPC2LI20
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete NRND
記憶體類型 Configuration PROM (non-volatile) Flash (in-system programmable)
記憶體容量 1.6 Mbit 1.6 Mb (1,572,864 bits)
組織 8-bit byte —
介面 Serial FPGA configuration + JTAG (IEEE 1149.1 / IEEE 1532) —
Programmability In-system programmable via JTAG —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (VCCSEL selectable) —
Cascade Support Yes - multi-device daisy chain —
Boundary Scan JTAG IEEE 1149.1 BST —
封裝 20-pin PLCC (J-lead) —
安裝類型 Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket-compatible)
工作溫度 [DATA_NEEDED: operating temperature range] -40 C to +85 C (Industrial)
MSL 等級 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL level]
RoHS 狀態 RoHS Compliant (per IC Components listing) [DATA_NEEDED: RoHS status]
Process Technology Low-power CMOS —
Target FPGAs APEX II, APEX 20K, Mercury, ACEX 1K, Cyclone, Stratix —
Programmable Type — In System Programmable (ISP)
功能 — Configuration PROM for SRAM-based FPGAs
Supply Voltage - Operating — 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing)
封裝 / 外殼 — 20-PLCC (J-lead, 9x9 mm)
Configuration Interface — Serial or Byte-wide (parallel)
Decompression — On-chip (supports compressed bitstreams)
JTAG / ISP Interface — IEEE 1532 (TCK, TMS, TDI, TDO)
Multi-Device Support — Yes (daisy-chain configuration)
User-Accessible Memory — Yes (unused flash available to user logic)

資料表與資源

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