EPC2LC20-U vs EPC2LC20 比較

詳細並排比較 EPC2LC20-U 由 Altera 與 EPC2LC20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2LC20-U EPC2LC20
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete NRND
單價 (USD) — $7.20
記憶體類型 Configuration PROM (Flash, in-system programmable) Non-volatile configuration PROM
記憶體容量 1.6 Mbit 1.6 Mbit
介面 Serial (4-wire Altera configuration) + JTAG (IEEE 1149.1) —
Max Configuration Clock 10 MHz —
Supply Voltage (VCC) 3.3 V (3.0 V to 3.6 V) —
Programmable In-system via JTAG —
Cascade Support Yes (multi-PROM for larger bitstreams) Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
封裝 20-PLCC (9x9) 20-pin PLCC (J-lead, 9x9 mm)
安裝類型 Surface Mount Surface Mount
工作溫度 [DATA_NEEDED: full operating temperature range] -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Supported FPGA Families ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
RoHS 狀態 [DATA_NEEDED: RoHS compliance status] Non-Compliant (original Altera Pb-containing part)
Lead-Free [DATA_NEEDED: lead-free status] —
MSL 等級 [DATA_NEEDED: moisture sensitivity level] —
Configuration Interface — Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Programming Interface — IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
Supply Voltage VCC — 3.0 V to 3.6 V (3.3-V operation)
ISP Voltage Range — 5.0 V or 3.3 V
Lead-Free Version — EPC2LC20N available as lead-free equivalent
Programming Support — Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan — IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

資料表與資源

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