EPC2LC20 vs EPC1LC120 比較
詳細並排比較 EPC2LC20 由 Altera 與 EPC1LC120 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2LC20 | EPC1LC120 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | NRND | 啟用中 |
| 記憶體類型 | Non-volatile configuration PROM | Serial Configuration Memory (Flash-based, non-volatile) |
| 記憶體容量 | 1.6 Mbit | — |
| Configuration Interface | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE | — |
| Programming Interface | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant | — |
| Supply Voltage VCC | 3.0 V to 3.6 V (3.3-V operation) | — |
| ISP Voltage Range | 5.0 V or 3.3 V | — |
| Supported FPGA Families | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 | APEX 20K, ACEX 1K, Cyclone, MAX, Mercury, Stratix-class |
| Cascade Support | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams | — |
| 封裝 | 20-pin PLCC (J-lead, 9x9 mm) | LQFP-120 (Low-profile Quad Flat Pack) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] | — |
| RoHS 狀態 | Non-Compliant (original Altera Pb-containing part) | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free Version | EPC2LC20N available as lead-free equivalent | — |
| Programming Support | Altera Programming Unit (APU), Quartus II, JTAG programmer | — |
| Boundary-Scan | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG | — |
| Memory Density | — | 1 Mbit |
| Serial Clock Frequency (DCLK) | — | 8 MHz |
| 介面 | — | Altera / Intel proprietary FPGA-configuration serial bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |
| 供應電壓 | — | [DATA_NEEDED: VCC range] |
| Programming | — | Factory / JTAG via Altera programming tools |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Mode | — | Serial configuration of SRAM-based FPGAs |
| Compatible Bitstream Width | — | Serial |