EPC2TC32U vs EPC2TC32-U-CAF48 比較

詳細並排比較 EPC2TC32U 由 Altera 與 EPC2TC32-U-CAF48 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2TC32U EPC2TC32-U-CAF48
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND 啟用中
功能 Serial Configuration Device for SRAM-based LUT FPGAs In-system programmable configuration PROM
記憶體容量 1.6 Mbit 1.6 Mb
Configuration Interface Altera Passive Serial (DCLK / DATA0 / nCONFIG / nSTATUS / CONF_DONE) —
JTAG Support Yes (IEEE 1149.1 boundary-scan, ISP) —
供應電壓 3.0 V to 3.6 V or 4.75 V to 5.25 V 3.3 V
工作溫度 -40 C to +85 C -40C to +85C (industrial, per data sheet)
封裝 32-pin QFP (CAF48, lead-free) 32-TQFP (7x7 mm)
安裝類型 Surface Mount Surface Mount
MSL 等級 [DATA_NEEDED: MSL level] —
RoHS 狀態 Compliant (lead-free / RoHS per distributor data) [DATA_NEEDED: RoHS status]
Lead-Free Finish Yes (U suffix) —
Supported FPGA Families Altera Stratix, Cyclone, APEX, ACEX, Mercury, Excalibur —
Configuration Mode Passive Serial (PS), JTAG —
Configuration Time [DATA_NEEDED: typical configuration time] —
Programming Cycles [DATA_NEEDED: minimum program/erase cycles] —
Data Retention [DATA_NEEDED: minimum data retention years] —
介面 — Serial synchronous (Altera FPGA configuration)
Programming Interface — IEEE 1149.1 JTAG
Control Pins — OE, nCS, DCLK
Cascadable — Yes (DATA output supports daisy-chain)
Storage Technology — EPROM
腳位數 — 32
DC Input Min — -0.3 V
DC Input Overshoot — 7.0 V for <100 mA, <20 ns
DC Input Undershoot — -2.0 V for <100 mA, <20 ns
Lead-Free — [DATA_NEEDED: lead-free status]

資料表與資源

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