EPM240ZM68C6N vs EPM240GM100C5N 比較
詳細並排比較 EPM240ZM68C6N 由 Intel 與 EPM240GM100C5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM240GM100C5N - 192-Cell MAX II G CPLD, 4.7ns, 100-MBGA | Intel / Altera
EPM240GM100C5N ✓ 啟用中規格比較
| 參數 | EPM240ZM68C6N | EPM240GM100C5N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX II Z (CPLD) | MAX II G |
| Macrocells | 192 | — |
| Logic Elements (LE) | 240 | — |
| Maximum Propagation Delay (tPD) | 7.5 ns | — |
| Internal Performance (fMAX) | 184.1 MHz | — |
| Process Technology | 0.18 µm | CMOS, Flash-based |
| User I/O Count | 80 | — |
| Number of I/O Banks | 4 | — |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (banked) | — |
| 封裝 | 68-ball Micro FBGA (MBGA-68) | 100-MBGA (Micro FineLine BGA), 6 x 6 mm |
| 安裝類型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Configuration Memory | On-chip flash (non-volatile, instant-on) | Non-volatile Flash |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | JTAG (IEEE 1149.1) - ISP |
| 工作溫度範圍 | -40°C to +85°C (commercial, 'C' suffix) | — |
| RoHS 狀態 | Compliant | — |
| Lead-Free Finish | Yes | — |
| MSL 等級 | 3 (per JEDEC J-STD-020) | 3 |
| Logic Elements | — | 240 (192 macrocells) |
| User I/Os | — | 80 |
| Pin-to-Pin Delay (tPD) | — | 4.7 ns |
| Ball Pitch | — | 0.5 mm |
| Supply Voltage - Core | — | 3.3 V |
| I/O Voltage Support | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multiVolt) |
| 工作溫度 | — | -40 C to +125 C |
| Lead Free / RoHS | — | Yes / Compliant |