EPM3512AFC256-18 vs EPM3256AFC256-7 比較
詳細並排比較 EPM3512AFC256-18 由 Altera 與 EPM3256AFC256-7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 Obsolete規格比較
| 參數 | EPM3512AFC256-18 | EPM3256AFC256-7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum User I/O Pins | 212 | — |
| Pin-to-Pin Delay (tPD1) | 18 ns | — |
| Global Clock Networks | 4 | — |
| VCCINT (Core Supply) | 3.0 V to 3.6 V (3.3 V typical) | — |
| VCCIO (I/O Supply) | 2.5 V or 3.3 V (MultiVolt) | — |
| 工作溫度 | [DATA_NEEDED: industrial/commercial grade] | 0 °C to 70 °C (Commercial) |
| Programming Technology | EEPROM (non-volatile) | — |
| In-System Programming | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) | — |
| 封裝 | 256-ball FineLine BGA (FCBGA) | FBGA-256 (FineLine BGA), 256 balls |
| Ball Pitch | 1.0 mm | — |
| RoHS 狀態 | [DATA_NEEDED: not specified in retrieved data] | [DATA_NEEDED: RoHS compliance status] |
| 安裝類型 | Surface Mount | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 256 |
| Usable Gates | — | 10,000 |
| User I/Os | — | 161 |
| Pin-to-Pin Logic Delay | — | 4.5 ns (max) |
| Counter Frequency | — | 227.3 MHz (max) |
| Propagation Delay (tpd) | — | 10 ns |
| Core Voltage | — | 3.3 V |
| I/O Compatibility | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) |
| Process Technology | — | CMOS EEPROM, 0.30 µm |
| In-System Programmability | — | IEEE Std. 1532-compliant 3.3-V ISP |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| Speed Grade | — | -7 |