EPM5032LC-25 vs EPM5032JC-20 比較
詳細並排比較 EPM5032LC-25 由 Altera 與 EPM5032JC-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032LC-25 | EPM5032JC-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Device Family | MAX 5000 | — |
| Architecture | PAL-type EPLD (Erasable Programmable Logic Device) | PAL-type AND-OR array with PIA interconnect |
| Technology | CMOS, UV-erasable / OTP | — |
| Macrocells | 32 | 32 |
| Product Terms | 320 | — |
| Dedicated Inputs | 7 | 8 |
| I/O Pins | 16 bidirectional | — |
| Total Inputs | 24 (7 dedicated + 16 I/O used as input) | 24 |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Maximum Internal Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V ±10% (4.5 V to 5.5 V) | — |
| I/O Standard | 5 V CMOS | — |
| 工作溫度 | 0 °C to +70 °C (commercial, "LC" suffix) | — |
| 封裝 | 28-pin PLCC (JEDEC S-PQCC-J28), 1.27 mm pitch | 68-pin JLCC (windowed ceramic) |
| 安裝類型 | Surface Mount, socket-compatible | — |
| Configuration Cell | Programmable interconnect array (PIA), OTP / UV-erasable | — |
| RoHS 狀態 | Not RoHS compliant (legacy Altera product) | — |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Family | — | MAX 5000 |
| Logic Array Blocks (LABs) | — | 1 |
| Product Terms (P-terms) | — | 320 |
| 最大時脈頻率 | — | 62.5 MHz |
| Setup Time | — | 10 ns |
| I/O Lines | — | 16 (bidirectional) |
| Process Technology | — | CMOS |
| Erase Method | — | UV (12V VPP + ultraviolet exposure) |
| Programming Voltage (VPP) | — | 12 V |
| 生命週期狀態 | — | Obsolete (legacy Altera MAX 5000) |