EPM5130JI vs EPM5130JC-1 比較
詳細並排比較 EPM5130JI 由 Altera 與 EPM5130JC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5130JI | EPM5130JC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable EPLD (CMOS EPROM) | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| 最大時脈頻率 | 33.3 MHz | — |
| Propagation Delay (tPD) | 55 ns | 40 ns |
| External Clock Inputs | 1 (shared input/clock) | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Process Technology | 0.75 micron CMOS EPROM | CMOS |
| 供應電壓 | 5 V (typical) | — |
| Input Logic Standard | TTL-compatible | — |
| Package Type | Ceramic J-Leaded Chip Carrier (JLCC) with UV window | — |
| 工作溫度 | Commercial (0C to +70C) | 0C to +70C (commercial) |
| Program/Erase Method | UV erasure through quartz window | — |
| RoHS 狀態 | Non-compliant (contains Pb in ceramic package) | [DATA_NEEDED: RoHS compliance] |
| Lifecycle | Obsolete - EOL by Altera/Intel | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 2,500 gates |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Dedicated Inputs | — | 19 |
| I/O Pins | — | 80 |
| 封裝 | — | 84-pin PLCC (J-lead) |
| 安裝類型 | — | Surface Mount |
| Programming Technology | — | UV-erasable EPROM (quartz window) |
| External Clock Pins | — | 1 global clock |