EPM5130WC-1 vs EPM5130JI 比較
詳細並排比較 EPM5130WC-1 由 Intel 與 EPM5130JI 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EPM5130WC-1 - 128-Macrocell 40ns UV CPLD, 100-pin CQFP | Intel (Altera) MAX 5000
EPM5130WC-1 Obsolete規格比較
| 參數 | EPM5130WC-1 | EPM5130JI |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | MAX 5000 | — |
| Manufacturer | Altera (now Intel) | — |
| Device Type | CPLD (Complex Programmable Logic Device) | UV-Erasable EPLD (CMOS EPROM) |
| Macrocell Count | 128 | — |
| Logic Array Blocks | Multiple LABs (per MAX 5000 architecture) | — |
| Propagation Delay (tpd) | 40 ns | — |
| 最大時脈頻率 | 50 MHz | 33.3 MHz |
| Erasure Method | UV (ultraviolet, windowed package) | — |
| Process Technology | CMOS EPROM | 0.75 micron CMOS EPROM |
| User I/O Pins | Up to 100 | — |
| Package Type | 100-pin Ceramic QFP (Windowed) | Ceramic J-Leaded Chip Carrier (JLCC) with UV window |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) |
| 供應電壓 | [DATA_NEEDED: VCC nominal] | 5 V (typical) |
| Programmable | Yes (UV-erasable, non-volatile) | — |
| Logic Family | MAX 5000 (Altera) | — |
| Configuration Memory | EPROM (on-chip) | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Non-compliant (contains Pb in ceramic package) |
| Family | — | MAX 5000 |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tPD) | — | 55 ns |
| External Clock Inputs | — | 1 (shared input/clock) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Input Logic Standard | — | TTL-compatible |
| Program/Erase Method | — | UV erasure through quartz window |
| Lifecycle | — | Obsolete - EOL by Altera/Intel |