EPM5192AGC84-15 vs EPM5192AGC84-20 比較
詳細並排比較 EPM5192AGC84-15 由 Altera 與 EPM5192AGC84-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192AGC84-15 | EPM5192AGC84-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable/OTP Complex PLD | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Internal Clock Frequency | 83.3 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Process Technology | CMOS | CMOS |
| Programmable Element | UV-Erasable EPROM cell | — |
| 封裝 | 84-pin Ceramic PGA (Pin Grid Array) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| 安裝類型 | Through-Hole | Through-Hole (Pin Grid Array socket) |
| 工作溫度 | Commercial (0C to +70C) - [DATA_NEEDED: military/industrial temp grade range] | — |
| RoHS 狀態 | [DATA_NEEDED: not declared in web data; ceramic PGA with UV window typically non-RoHS] | [DATA_NEEDED: RoHS compliance] |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Erasure Method | — | UV-Erasable (with OTP window) |
| Operating Temperature Grade | — | Commercial |
| 供應電壓 | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |