EPM5192JC vs EPM5192JC-ES 比較
詳細並排比較 EPM5192JC 由 Intel 與 EPM5192JC-ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC | EPM5192JC-ES |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Series | EPM5192 (Classic / MAX-class) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect Architecture | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| 封裝 | 68-pin PLCC (JC) windowed ceramic | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) |
| 安裝類型 | Surface Mount | Surface Mount |
| Programming Method | UV-erase + EPROM programmer | — |
| Non-Volatile Configuration | Yes (EPROM cell array) | — |
| Logic Family | Classic CPLD (EPM5xxx series) | — |
| 工作溫度 | [DATA_NEEDED: commercial / industrial / military grade] | [DATA_NEEDED: operating temperature range for ES grade] |
| 供應電壓 | [DATA_NEEDED: VCC nominal] | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | [DATA_NEEDED: tpd spec by speed grade] | — |
| RoHS 狀態 | [DATA_NEEDED: original Altera marking not RoHS] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Device Type | — | CPLD (EPLD) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Configuration Memory | — | EPROM (UV-erasable, one-time programmable for JC-ES) |
| Technology | — | CMOS |
| Programming | — | Altera MAX+PLUS II or compatible programmer |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Note | — | Datasheet source: Altera MAX 5000 family document, 52 pages |