EPM5192JC vs EPM5192JI 比較
詳細並排比較 EPM5192JC 由 Intel 與 EPM5192JI 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC | EPM5192JI |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Series | EPM5192 (Classic / MAX-class) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect Architecture | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| 封裝 | 68-pin PLCC (JC) windowed ceramic | 84-pin PLCC (windowed, J-suffix ceramic) |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket recommended for UV erasure) |
| Programming Method | UV-erase + EPROM programmer | Altera MAX 5000 programming algorithm (device programmer) |
| Non-Volatile Configuration | Yes (EPROM cell array) | — |
| Logic Family | Classic CPLD (EPM5xxx series) | — |
| 工作溫度 | [DATA_NEEDED: commercial / industrial / military grade] | -40 C to +125 C (industrial, I-suffix) |
| 供應電壓 | [DATA_NEEDED: VCC nominal] | 4.75 V to 5.25 V (nominal 5 V) |
| Propagation Delay | [DATA_NEEDED: tpd spec by speed grade] | — |
| RoHS 狀態 | [DATA_NEEDED: original Altera marking not RoHS] | [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant] |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (UV-erasable CMOS Programmable Logic Device) |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| Propagation Delay (tpd) | — | 55 ns |
| Technology | — | CMOS EPROM, UV-erasable |
| Erasure Method | — | UV exposure through windowed package |