EPM5192JC2 vs EPM5192JC-ES 比較
詳細並排比較 EPM5192JC2 由 Intel 與 EPM5192JC-ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC2 | EPM5192JC-ES |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (EPLD) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Usable Gates (equivalent) | 6000 | — |
| Maximum User I/O | 64 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs | 1 (with shared input/clock capability) | — |
| 最大時脈頻率 | 50 MHz | — |
| Propagation Delay (tPD) | 45 ns (speed grade -2) | — |
| Process Technology | CMOS, UV-erasable | — |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| 封裝 | PLCC-68 (JC) | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) |
| 安裝類型 | Surface Mount (socketable PLCC) | Surface Mount |
| Programming | Altera Master Programmer / ByteBlaster via JTAG-style interface | Altera MAX+PLUS II or compatible programmer |
| Device Family | — | MAX 5000 |
| Configuration Memory | — | EPROM (UV-erasable, one-time programmable for JC-ES) |
| Technology | — | CMOS |
| 工作溫度 | — | [DATA_NEEDED: operating temperature range for ES grade] |
| 供應電壓 | — | [DATA_NEEDED: VCC nominal] |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Note | — | Datasheet source: Altera MAX 5000 family document, 52 pages |