EPM5192LC-2 vs EPM5192LC 比較
詳細並排比較 EPM5192LC-2 由 Altera 與 EPM5192LC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-2 | EPM5192LC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | 64 |
| Dedicated Input Pins | 7 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 45 ns (typical, -2 speed grade) | 55 ns (typical, commercial) |
| Maximum Internal Frequency | 50 MHz | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS | CMOS, UV-erasable/OTP EPROM configuration |
| 封裝 | PQCC-84 (PLCC-84, J-lead, surface mount) | JLCC-68 (windowed ceramic, LC suffix) |
| Programming | Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) | — |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | — |
| 供應電壓 | 5 V (typical MAX 5000 family) | — |
| RoHS 狀態 | [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS] | [DATA_NEEDED: RoHS status] |
| Dedicated Inputs | — | 7 |
| Global Clock Inputs | — | 1 |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA), fixed delay |
| Boundary-Scan Support | — | JTAG IEEE 1149.1 |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |
| Operating Temperature (commercial) | — | 0C to +70C |
| 安裝類型 | — | Surface Mount |