EPM5192LI84 - 192-Macrocell MAX 5000 CPLD 84-PLCC | Altera
MPN： EPM5192LI84 ✗ 停產EPM5192LI84 概覽
A Complex Programmable Logic Device (CPLD) is a non-volatile, flash- or EPROM-based logic device that implements glue logic, state machines, bus decoding, and interface bridging functions between fixed-function ICs. The MAX 5000 family sits within Altera's broader programmable logic hierarchy: CPLD -> Programmable Logic Device (PLD) -> Programmable Logic -> Digital Semiconductor. CPLDs are distinguished from FPGAs by their deterministic timing, instant-on non-volatile configuration, and pin-to-pin delay specifications that do not vary with logic utilization.
Key features of the EPM5192LI84 include 192 macro cells, 3.75 K usable gates, 64 user I/O pins, a JTAG-based in-system programming interface (not all variants), and an OTP/UV-erasable configuration memory that retains pattern data without external storage. The PLCC-84 socket-compatible package is removable for laboratory UV erasure and re-programming, which historically made this family attractive for prototyping and low-volume industrial designs.
The device uses Altera's classic MAX architecture with an EEPROM/EPROM-based AND plane feeding a fixed OR-plane macro cell fabric. Each macro cell contains a programmable flip-flop, product-term selection logic, and an I/O control block. Logic synthesis is performed with Altera's MAX+PLUS II or Quartus design tools, which are still maintained in legacy mode for industrial customers servicing long-lifecycle equipment.
Typical applications include legacy industrial control replacement, military/aerospace avionics refresh (via the JM/883 MIL-STD-883B variants), telecommunications backplane glue logic, and bus-interface bridging in long-lifecycle OEM equipment. The OTP nature makes the EPM5192LI84 suited to designs where the pattern is finalized and re-programming is rarely required.
When designing with this part, note that the LI84 device does NOT support in-system programmability - the JTAG port is absent on most MAX 5000 OTP variants, so a stand-alone programmer (e.g. Altera Logic Programmer or compatible third-party tools) is required. Use the LC84 (windowed ceramic) variant if UV erasure is anticipated, and reserve proper decoupling on every VCC/ground pin pair to meet the 5 V TTL I/O switching noise budget.
This page synthesizes distributor pricing snapshots, same-brand pin-compatible variants already published on XAIPART (EPM5192LI family members), and practical design notes not found in the legacy Altera datasheet alone.
直接替換替代品，適用於 EPM5192LI84 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EPM5192LI84 （相同外形與佔位） — 差異在於 Mounting Type, Device Type, Package, Process Technology, Programmability.
EPM5192LC84
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5192LI-1
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5192LI-2
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5192GI84
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5192ALI84-15
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5192ALI84-20
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EPM5192LI84 最大額定值與電氣特性
| Device Family | MAX 5000 |
| Product Type | UV-Erasable/OTP Complex PLD (CPLD) |
| Usable Gates | 3,750 gates |
| Macro Cells | 192 |
| Maximum Toggle Frequency | 40 MHz |
| Pin-to-Pin Delay (tPD) | 25 ns |
| Supply Voltage (VCC) | 5 V (single supply) |
| User I/O Pins | 64 (max) |
| 工作溫度範圍 | -40 °C to +85 °C (industrial) |
| Package Type | 84-pin PLCC (J-lead, package code J84/QCCJ) |
| 安裝類型 | Surface Mount (socket-compatible) |
| Configuration Memory | OTP / UV-erasable EPROM |
| Programming Method | Stand-alone programmer (no JTAG on LI84 OTP variant) |
| Logic Compatibility | TTL-compatible I/O |
EPM5192LI84 腳位配置
| 腳位 1 | I/O — User I/O pin (macrocell input/output) |
| 腳位 2 | I/O — User I/O pin |
| 腳位 3 | I/O — User I/O pin |
| 腳位 4 | I/O — User I/O pin |
| 腳位 5 | I/O — User I/O pin |
| 腳位 6 | I/O — User I/O pin |
| 腳位 7 | I/O — User I/O pin |
| 腳位 8 | I/O — User I/O pin |
| 腳位 9 | I/O — User I/O pin |
| 腳位 10 | I/O — User I/O pin |
| 腳位 11 | GND — Ground |
| 腳位 12 | I/O — User I/O pin |
| 腳位 13 | I/O — User I/O pin |
| 腳位 14 | I/O — User I/O pin |
| 腳位 15 | I/O — User I/O pin |
| 腳位 16 | I/O — User I/O pin |
| 腳位 17 | I/O — User I/O pin |
| 腳位 18 | I/O — User I/O pin |
| 腳位 19 | I/O — User I/O pin |
| 腳位 20 | I/O — User I/O pin |
| 腳位 21 | I/O — User I/O pin |
| 腳位 22 | GND — Ground |
| 腳位 23 | I/O — User I/O pin |
| 腳位 24 | I/O — User I/O pin |
| 腳位 25 | I/O — User I/O pin |
| 腳位 26 | I/O — User I/O pin |
| 腳位 27 | I/O — User I/O pin |
| 腳位 28 | I/O — User I/O pin |
| 腳位 29 | I/O — User I/O pin |
| 腳位 30 | I/O — User I/O pin |
| 腳位 31 | I/O — User I/O pin |
| 腳位 32 | I/O — User I/O pin |
| 腳位 33 | GND — Ground |
| 腳位 34 | I/O — User I/O pin |
| 腳位 35 | I/O — User I/O pin |
| 腳位 36 | I/O — User I/O pin |
| 腳位 37 | I/O — User I/O pin |
| 腳位 38 | I/O — User I/O pin |
| 腳位 39 | I/O — User I/O pin |
| 腳位 40 | I/O — User I/O pin |
| 腳位 41 | I/O — User I/O pin |
| 腳位 42 | I/O — User I/O pin |
| 腳位 43 | I/O — User I/O pin |
| 腳位 44 | GND — Ground |
| 腳位 45 | I/O — User I/O pin |
| 腳位 46 | I/O — User I/O pin |
| 腳位 47 | I/O — User I/O pin |
| 腳位 48 | I/O — User I/O pin |
| 腳位 49 | I/O — User I/O pin |
| 腳位 50 | I/O — User I/O pin |
| 腳位 51 | I/O — User I/O pin |
| 腳位 52 | I/O — User I/O pin |
| 腳位 53 | I/O — User I/O pin |
| 腳位 54 | I/O — User I/O pin |
| 腳位 55 | GND — Ground |
| 腳位 56 | I/O — User I/O pin |
| 腳位 57 | I/O — User I/O pin |
| 腳位 58 | I/O — User I/O pin |
| 腳位 59 | I/O — User I/O pin |
| 腳位 60 | I/O — User I/O pin |
| 腳位 61 | I/O — User I/O pin |
| 腳位 62 | I/O — User I/O pin |
| 腳位 63 | I/O — User I/O pin |
| 腳位 64 | I/O — User I/O pin |
| 腳位 65 | I/O — User I/O pin |
| 腳位 66 | GND — Ground |
| 腳位 67 | I/O — User I/O pin |
| 腳位 68 | I/O — User I/O pin |
| 腳位 69 | I/O — User I/O pin |
| 腳位 70 | I/O — User I/O pin |
| 腳位 71 | I/O — User I/O pin |
| 腳位 72 | I/O — User I/O pin |
| 腳位 73 | I/O — User I/O pin |
| 腳位 74 | I/O — User I/O pin |
| 腳位 75 | I/O — User I/O pin |
| 腳位 76 | I/O — User I/O pin |
| 腳位 77 | GND — Ground |
| 腳位 78 | I/O — User I/O pin |
| 腳位 79 | I/O — User I/O pin |
| 腳位 80 | I/O — User I/O pin |
| 腳位 81 | I/O — User I/O pin |
| 腳位 82 | I/O — User I/O pin |
| 腳位 83 | I/O — User I/O pin |
| 腳位 84 | I/O — User I/O pin |
典型應用
EPM5192LI84 適用於 6 應用s: Legacy Industrial Glue Logic Replacement, Telecommunications Backplane Bus Bridging, Military/Avionics Refresh with MIL-STD-883B Variants, Bus Decoding and Chip-Select Generation, State Machine and Protocol Implementation, Long-Lifecycle OEM Production Sustainment.
Legacy Industrial Glue Logic Replacement
The EPM5192LI84 is widely used to replace discrete 74LS/74F glue-logic ICs in long-lifecycle industrial control boards where the original programmable logic has failed after 20+ years of service. With 192 macro cells, 3,750 usable gates, and 64 user I/O pins, it absorbs the address decoding, chip-select generation, and handshake-stretching functions that previously required 8-15 discrete TTL packages. The OTP nature means the finalized pattern is fixed for the equipment's lifetime - ideal for OEM equipment that must remain bit-for-bit identical across decades of production. Engineers benefit from consolidating 74-series logic into a single 84-pin PLCC socketed part, simplifying board test and reducing assembly cost.
推薦
Telecommunications Backplane Bus Bridging
In legacy telecom backplanes (e.g. T1/E1 multiplexers, SDH/SONET tributary cards, central-office line cards), the EPM5192LI84 serves as a 5 V-TTL bus bridge between parallel processor buses and serial framer ICs. Its 25 ns pin-to-pin delay accommodates 40 MHz backplane operation without timing closure issues, and the deterministic delay model makes it suitable for asynchronous handshake protocols. The industrial temperature grade (-40 °C to +85 °C) and 5 V tolerance allow direct interface to legacy bus drivers like the AM26LS31/32 and DS26F31/32. The 84-pin PLCC socket allows field replacement without re-soldering, which is critical for telecom central-office maintenance windows.
推薦
Military/Avionics Refresh with MIL-STD-883B Variants
For avionics and defense refresh programs, the JM/883 and GM/883B screened versions of the EPM5192 share the same 84-pin PLCC pinout but add MIL-STD-883B processing for temperature, vibration, and hermeticity. The EPM5192LI84 itself is industrial-grade; designers seeking MIL-grade drop-in replacement can use EPM5192JM/883B or EPM5192GM/883B in the same PLCC-84 footprint. The 192-macrocell capacity suits mission-computer interface boards, MIL-STD-1553 bus monitor glue, and ARINC 429 line-card logic. PLCC packaging allows conformal coating and easy field replacement on avionics LRUs.
推薦
Bus Decoding and Chip-Select Generation
A primary application of the EPM5192LI84 is generating chip-select signals and address decoding for microprocessor memory maps. With 64 user I/O pins and 192 macro cells, the device can decode a full 24-bit address bus and generate up to 16-32 chip-select outputs with individual wait-state insertion. The OTP configuration makes it immune to soft errors and bus contention from mis-configuration, a frequent issue with flash-based CPLDs in noisy industrial environments. The 5 V TTL I/O matches legacy 80C186, 68SEC000, and 80C51 peripheral buses commonly found in factory automation and process control.
推薦
State Machine and Protocol Implementation
The EPM5192LI84 is well-suited to implementing synchronous state machines for serial protocols (SPI, I2C, UART bit-banging, custom proprietary protocols) in industrial equipment where dedicated peripheral ICs are unavailable. Each macro cell provides a D-flip-flop with individual clock-enable and clear, allowing complex FSMs with 50-80 states to be implemented cleanly. The deterministic 25 ns pin-to-pin delay ensures protocol timing margins are met across the full industrial temperature range. The PLCC socket allows post-assembly programming verification - the user programs the OTP, installs it, and verifies protocol operation in-system.
推薦
Long-Lifecycle OEM Production Sustainment
OEMs producing 15-30 year lifecycle equipment (medical imaging, semiconductor test gear, railway signaling, military radios) use the EPM5192LI84 because the OTP pattern guarantees bit-for-bit identical functionality across every unit ever shipped - no configuration drift, no flash bit-flip, no firmware-update risk. The Altera MAX 5000 datasheet guarantees 20-year data retention in OTP mode. Independent distributors (Jotrin, FPGAkey, Win Source) continue to stock the part for these sustainment programs. The 84-pin PLCC is socket-compatible across production runs, simplifying board rework and field upgrades.
推薦
推薦產品摘要
工程參考資料，適用於 EPM5192LI84 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EPM5192LC84 | EPM5192LI-1 | EPM5192LI-2 | EPM5192GI84 | EPM5192ALI84-15 | EPM5192ALI84-20 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 84-pin PLCC (J-lead, QCCJ) | 84-pin PLCC (J-lead, QCCJ) - same | 84-pin PLCC (J-lead, QCCJ) - same | 84-pin PLCC (J-lead, QCCJ) - same | 84-pin PLCC (J-lead, QCCJ) - same | 84-pin PLCC (J-lead, QCCJ) - same | 84-pin PLCC (J-lead, QCCJ) - same |
| Macro Cells | 192 | 192 | 192 | 192 | 192 | 192 | 192 |
| Usable Gates | 3,750 | 3,750 | 3,750 | 3,750 | 3,750 | 3,750 | 3,750 |
| Pin-to-Pin Delay (tPD) | 25 ns | 25 ns | ~15 ns | ~10 ns | ~15 ns | 15 ns | 20 ns |
| User I/O Pins | 64 | 64 | 64 | 64 | 64 | 64 | 64 |
| Configuration Memory | OTP / UV-erasable | UV-erasable (ceramic window) | OTP | OTP | OTP | OTP | OTP |
| Operating Temperature | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C | -40 °C to +85 °C |
主要差異化特點
- OTP / UV-erasable configuration memory with 20-year data retention (對比EPM5192LC84)
- Industrial temperature range -40 °C to +85 °C (對比EPM5192LI-1)
- 84-pin PLCC socket-compatible package for field replacement (對比EPM5192GM/883B)
設計說明
Estimated: The EPM5192LI84 draws approximately 200-400 mA from a single 5 V supply depending on toggle activity and I/O switching. Provide one 0.1 µF ceramic decoupling capacitor per VCC/GND pin pair (8 caps for the 84-pin PLCC) plus a single 10 µF bulk tantalum or electrolytic on the 5 V rail. Place the 0.1 µF caps within 3 mm of each VCC pin to suppress TTL switching transients. The device has no power-sequencing requirement relative to other 5 V logic, but ensure the 5 V rail ramps monotonically to avoid EEPROM cell stress during initial power-up programming.
Use a through-hole PLCC-84 socket (e.g. 3M 8484 or equivalent) so the OTP device can be programmed externally and replaced without de-soldering. Maintain 0.1 inch (2.54 mm) pitch land pattern with 1.0-1.5 mm drill pads for socket compatibility. Route all 64 user I/O signals with 50 Ω controlled impedance if any signal exceeds 25 MHz; otherwise standard TTL routing is sufficient. Keep the 84-pin PLCC socket away from board edges to avoid mechanical stress and provide at least 0.5 inch clearance on all sides for programming clip access.
Critical pitfalls: (1) The EPM5192LI84 is OTP - it cannot be re-programmed. Use the EPM5192LC84 (ceramic-windowed) variant for development and switch to LI84 only for production. (2) The LI84 has NO JTAG port - programming requires a stand-alone Altera Logic Programmer (e.g. PL-ASAP) BEFORE board installation or with a socket adapter. (3) Do not mix EPM5192 (MAX 5000, 5 V) with MAX 7000 (EEPROM, 5 V) or MAX V (1.8 V core) - pinouts are NOT compatible despite same PLCC-84 footprint. (4) Verify programming voltage timing on the stand-alone programmer; over-voltage on the OTP programming pins will permanently damage the device.
合規資訊
RoHS/REACH/lead-free status not stated in the Verified Web Data; pre-2005 Altera MAX 5000 OTP plastic parts were typically manufactured with SnPb finish (non-RoHS). For RoHS-compliant alternatives in the same footprint, contact Altera/Intel FPGA regarding lead-free re-finished inventory (rare for obsolete OTP parts).
